1、E DA课程设计 信息与计算机工程学院 电子信息专业3班 安吉旺 20082966 一设计要求消除本设计中的PC模块,代之以存储器中的mem20,也就是mem20就是pc(这样做的好处是pc这时候变成了可寻址单元, (可以直接修改pc实现程序的绝对跳转)。另外,将冯诺依曼(vonNeuman)的体系结构改成哈佛结构,将编写机器码并且给出仿真波形。二结构说明冯诺依曼(vonNeuman)的体系结构,将指令、数据、地址存储在同一存储器中,统一编址,依靠指令计数器提供的地址来区分是指令、数据还是地址。取指令和取数据都访问同一存储器。而哈佛结构是将程序和数据存储在不同的存储空间中,即程序存储器和数据存
2、储器是两个相互独立的存储器,每个存储器独立编址,独立访问。 三程序代码1控制器代码 module control(input clock,input reset,output reg s0, / fetch instructionoutput reg s1, / decodeoutput reg s2, / read memory data for processoutput reg s3, / enable alu to computeoutput reg s4, / write to memory if nessaryoutput reg s5, / increase pc/output
3、reg addrsel,output reg instr_add,output reg instr_sub,output reg instr_and,output reg instr_pass,input 2:0 opcode);parameter LDA=3b000,STA=3b001,ADD=3b010, SUB=3b011,AND=3b100,HLT=3b101;/ JMP=3b110, JZF=3b111;reg 2:0 cnt;always(posedge clock or posedge reset)if(reset)cnt = 0;elseif(cnt = 5) cnt = 0;
4、else cnt = cnt +1;always*begincase(cnt)0:begin/ fetch instructions0 =1;s1=0;s2=0;s3=0;s4=0;s5=0;/addrsel=0; end1:begin/ decodes0 =0;s1=1;s2=0;s3=0;s4=0;s5=0;/addrsel=0;end2:begin/ read memory data for process if nessary s0 =0;s1=0;/*s2=1;*/s3=0;s4=0;s5=0; /addrsel=1;if(opcode = LDA )|(opcode = ADD)|
5、(opcode = SUB)|(opcode = AND)s2=1;elses2=0;end3:begin /enable ALU to computes0 =0;s1=0;s2=0;s3=1;s4=0;s5=0; / addrsel=1; if(opcode = LDA) begin instr_add =0;instr_sub =0;instr_and =0; instr_pass=1; endelse if(opcode = ADD) begin instr_add =1;instr_sub =0;instr_and =0; instr_pass=0; endelse if(opcode
6、 = SUB) begin instr_add =0;instr_sub =1;instr_and =0; instr_pass=0; endelse if(opcode = AND) begin instr_add =0;instr_sub =0;instr_and =1; instr_pass=0; endelse if(opcode = STA) begin instr_add =0;instr_sub =0;instr_and =0; instr_pass=0; endelse begin instr_add =0;instr_sub =0;instr_and =0; instr_pa
7、ss=0; endend4:begin/ write to memory if nessarys0 =0;s1=0;s2=0;s3=0;/*s4=1;*/s5=0; /addrsel=1;if(opcode = STA) s4=1;else s4=0;end5:begin s0 =0;s1=0;s2=0;s3=0;s4=0;s5=1;/addrsel=1; endendcaseendendmodule2.存储器代码(1)module memory(clock,reset,addr,din,dout,rd,wr,IN,OUT,pc,pc_en);input clock,reset;input p
8、c_en;input 7:0 din;input 4:0 addr;output reg 7:0 dout;input rd,wr; input 7:0 IN; output reg 7:0 OUT;output 4:0 pc; wire 7:0pc_next;assign pc_next=mem20;/reg7:0 mem31:0;reg7:0 mem30:0;always(posedge clock or posedge reset)if(reset)beginmem0 =b1;/00001011; /LDA 11mem1 =b1;/01001100; /ADD 12mem2 =b1;/0
9、0101101; /STA 13/mem3 =b00001011; /LDA 11mem3 =b1;/00011111; /LDA 31mem4 =b1;/10001100; /AND 12/mem5 =b00101110; /STA 14mem5 =b1;/00111111; /STA 31mem6 =b1;/00001011; /LDA 11mem7 =b1;/01101100; /SUB 12/mem8 =b00101111; /STA 15 mem8 =b1;/00110100; /sta pcmem9 =b1;/10100000; /HLTmem10=b1;mem11=b10101010;mem12=b01010101;mem13=b1;mem14=b1;mem15=b1;mem16=b1;mem17=b1;mem18=b1;mem19=b1;mem20=b0;mem21=b00001011;mem22=b01001100;mem23=b00101101; mem24=b1;mem25=b1;mem2
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