300mA的超低噪声小封装超高速CMOS LDO稳压器LP3984.docx

1、300mA的超低噪声小封装超高速CMOS LDO稳压器LP3984 300mA,Ultra-low noise, Small Package Ultra-Fast CMOS LDO RegulatorGeneral Description The LP3984 is designed for portable RF and wireless applications with demanding performance and space requirements. The LP3984 performance is optimized for battery-powered systems

2、to deliver ultra low noise and low quiescent current. A noise bypass pin is available for further reduction of output noise. Regulator ground current increases only slightly in dropout, further prolonging the battery life. The LP3984 also works with low-ESR ceramic capacitors, reducing the amount of

3、 board space necessary for power applications, critical in hand-held wireless devices. The LP3984 consumes less than 0.01A in shutdown mode and has fast turn-on time less than 50s. The other features include ultra low dropout voltage, high output accuracy, current limiting protection, and high rippl

4、e rejection ratio. It is available in the 5-lead of SOT23-5 packages.Ordering Information LP3984 F: Pb-Free Package Type B5: SOT23-5 Output Voltage Type 12: 1.2V 13: 1.3V 15: 1.5V 18: 1.8V 25: 2.5V28: 2.8V2H: 2.85V30: 3.0V 33: 3.3VFeatures Ultra-Low-Noise for RF Application 2V- 6.5V Input Voltage Ra

5、nge Low Dropout : 200mV 300mA 1.2V, 1.3V,1.5V, 1.8V, 2.5V, 2.8V 3.0V and 3.3V Fixed 300mA Output Current, 550mA Peak Current High PSSR:-73dB at 1KHz 2.5V300mACurrent LimitILIMRLOAD = 1360400mAQuiescent CurrentIQVEN 1.2V, IOUT = 0mA75130ADropout VoltageVDROPIOUT = 200mA, VOUT 2.8V120150mVIOUT = 300mA

6、, VOUT 2.8V200260Line RegulationVLINEVIN = (VOUT + 1V) to 5.5V, IOUT = 1mA0.3%Load RegulationLOAD1mA IOUT 1F on the LP3984 input and the amount of capacitance can be increased without limit. The input capacitor must be located a distance of not more than 0.5 inch from the input pin of the IC and ret

7、urned to a clean analog ground. Any good quality ceramic or tantalum can be used for this capacitor. The capacitor with larger value and lower ESR (equivalent series resistance) provides better PSRR and line-transient response. The output capacitor must meet both requirements for minimum amount of c

8、apacitance and ESR in all LDOs application. The LP3984 is designed specifically to work with low ESR ceramic output capacitor in space-saving and performance consideration. Using a ceramic capacitor whose value is at least 1F with ESR is 25m on the LP3984 output ensures stability. The LP3984 still w

9、orks well with output capacitor of other types due to the wide stable ESR range. Figure 1 shows the curves of allowable ESR range as a function of load current for various output capacitor values. Output capacitor of larger capacitance can reduce noise and improve load transient response, stability,

10、 and PSRR. The output capacitor should be located not more than 0.5 inch from the VOUT pin of the LP3984 and returned to a clean analog ground. Start-up Function Enable Function The LP3984 features an LDO regulator enable/disable function. To assure the LDO regulator will switch on, the EN turn on c

11、ontrol level must be greater than 1.4 volts. The LDO regulator will go into the shutdown mode when the voltage on the EN pin falls below 0.4 volts. For to protecting the system, the LP3984 have a quick-discharge function. If the enable function is not needed in a specific application, it may be tied

12、 to VIN to keep the LDO regulator in a continuously on state. Bypass Capacitor and Low Noise Connecting a 22nF between the BP pin and GND pin significantly reduces noise on the regulator output, it is critical that the capacitor connection between the BP pin and GND pin be direct and PCB traces shou

13、ld be as short as possible. There is a relationship between the bypass capacitor value and the LDO regulator turn on time. DC leakage on this pin can affect the LDO regulator output noise and voltage regulation performance. Thermal ConsiderationsThermal protection limits power dissipation in LP3984.

14、 When the operation junction temperature exceeds 165C, the OTP circuit starts the thermal shutdown function turn the pass element off. The pass element turns on again after the junction temperature cools by 30C. For continue operation, do not exceed absolute maximum operation junction temperature 12

15、5C. The power dissipation definition in device is : PD = (VINVOUT) x IOUT + VIN x IQ The maximum power dissipation depends on the thermal resistance of IC package, PCB layout, the rate of surroundings airflow and temperature difference between junction to ambient. The maximum power dissipation can b

16、e calculated by following formula :PD(MAX) = ( TJ(MAX) TA ) /JA Where TJ(MAX) is the maximum operation junction temperature 125C, TA is the ambient temperature and the JA is the junction to ambient thermal resistance. For recommended operating conditions specification of LP3984, where TJ(MAX) is the

17、 maximum junction temperature of the die (125C) and TA is the maximum ambient temperature. The junction to ambient thermal resistance (JA is layout dependent) for SOT23-5 package is 250C/W. PD(MAX) = (125C25C) / 250 = 400mW (SOT23-5) PD(MAX) = (125C25C) / 165 = 606mW (with PCB PAD)The maximum power dissipation depends on operating ambient temperature for fixed TJ(MAX) and thermal resistance JA.Packaging Information