湘潭大学计算机原理试验四多周期MIPSCPU存储器试验预习报告解析.docx

1、湘潭大学计算机原理试验四多周期MIPSCPU存储器试验预习报告解析实验四 多周期 MIPS CPU + 存储器实验一实验目的1、深入理解 MIPS CPU 指令系统的功能和工作原理；2、掌握多周期 CPU 的工作原理和逻辑功能实现；3、熟练掌握用 Verilog HDL 语言设计多周期存储器的方法；4、熟练掌握对多周期存储器的仿真实验验证和硬件测试两种调试方法；5、通过对多周期 CPU 的运行情况进行观察和分析，进一步加深理解。二实验设备硬件： 现代计算机组成原理实验系统（兼）Nios 32 位嵌入式系统实验开发平台EP1C12Q240Core（TM）i3-3240 CPU3.40GHz 3.

2、39GHz 1.91GB的内存软件： QuartusII 13.0sp1Microsoft Windows xp三实验内容1、设计一个 32 位 MIPS 多周期 CPU : 至少运行下列的 6 类 32 条 MIPS 指令。（1） and、 sub、addi（2 and、 0r、xor、 andi、 ori 、xori（3 sll 、srl 、sra（4） beq、 bne、（5） j、 jr（6） lw 、 sw2.设计一个存储器四实验原理与步骤实现上述原理框图根据功能将其分划分为控制单元 (cunit) 、执行单元 (eunit) 、指令单元 (iunit)以及存储单元 (munit)

3、四大模块。(1) .控制单元 (cunit)行等工作。主要由指令译码器控制器 (outputs control) 、算术逻辑运算控制器 (ALU control) 两 个子模块组成。(2).执行单元 (eunit) 主要由寄存器堆 (registers)和算术逻辑单元 (ALU) 两个子模块组成。其 MIPS 系统的寄存器堆由 32 个 32ALU 等逻辑运算。指令单元 (iunit) 的作用是决定下一条指令的地址 PC(3).存储单元 (munit)由存储器 (memory) 、指令寄存器 (instruction register) 和存储数据寄存 器 (memory data regis

4、ter) 组成。五实验源代码寄存器元件代码：module regfile (rna,rnb,d,wn,we,clk,clrn,qa,qb);input4:0rna,rnb,wn;input31:0d;inputwe,clk,clrn;output31:0qa,qb;reg31:0register 1:31;/r1-r31assignqa = (rna =0) ? 0 :registerrna;/readassignqb = (rnb =0) ? 0 :registerrnb;/readalways (posedge clk or negedge clrn) beginif (clrn = 0)

5、 begin /resetinteger i;for (i=1; i32; i=i+1) registeri = 0;endelse beginif (wn != 0) & (we = 1) /writeregisterwn = d;end end endmodule32 位四选一选择器：module mux4x32 (a0,a1,a2,a3,s,y);input 31:0a0,a1,a2,a3;input 1:0s;output 31:0y;function 31:0select;input 31:0a0,a1,a2,a3;input 1:0s;case (s)2b00:select= a0

6、;2b01:select= a1;2b10:select= a2;2b11:select= a3;endcase endfunction5 位二选一选择器： module mux2x5 (a0,a1,s,y);input 4:0 a0,a1;input s;output4:0 y;assign y = s ? a1 : a0;endmodule32 位二选一选择器： module mux2x32 (a0,a1,s,y);input31:0a0,a1;inputs;output31:0y;assigny = s ? a1 : a0;endmodule存储器元件：module mcmem (clk

7、, dataout, datain, addr, we, inclk, outclk);input31:0datain;input31:0addr;inputclk, we, inclk, outclk;output31:0dataout;wirewrite_enable = we & clk;lpm_ramdqram(.data(datain),.address(addr7:2),.we(write_enable),.inclock(inclk),.outclock(outclk),.q(dataout);defparamram.lpm_width= 32;defparamram.lpm_w

8、idthad= 6;defparamram.lpm_indata= registered;defparamram.lpm_outdata= registered;defparamram.lpm_file= mcmem.mif;defparamram.lpm_address_control= registered;endmodule控制部件：module mccu (op, func, z, clock, resetn, wpc, wir, wmem, wreg, iord, regrt, m2reg, aluc, shift, alusrca, alusrcb, pcsource, jal,

9、sext, state);input 5:0 op, func;input z, clock, resetn;output reg wpc, wir, wmem, wreg, iord, regrt, m2reg;output reg 3:0 aluc;output reg 1:0 alusrcb, pcsource;output reg shift, alusrca, jal, sext;output reg 2:0 state;reg 2:0 next_state;parameter2:0 sif =3b000,/ IF statesid =3b001,/ ID statesexe =3b

10、010,/ EXE statesmem= 3b011,/ MEM stateswb =3b100;/ WB statewire r_type,i_add,i_sub,i_and,i_or,i_xor,i_sll,i_srl,i_sra,i_jr;wire i_addi,i_andi,i_ori,i_xori,i_lw,i_sw,i_beq,i_bne,i_lui,i_j,i_jal; and(r_type,op5,op4,op3,op2,op1,op0); and(i_add,r_type, func5,func4,func3,func2,func1,func0); and(i_sub,r_t

11、ype, func5,func4,func3,func2, func1,func0); and(i_and,r_type, func5,func4,func3, func2,func1,func0); and(i_or, r_type, func5,func4,func3, func2,func1, func0); and(i_xor,r_type, func5,func4,func3, func2, func1,func0); and(i_sll,r_type,func5,func4,func3,func2,func1,func0); and(i_srl,r_type,func5,func4

12、,func3,func2, func1,func0); and(i_sra,r_type,func5,func4,func3,func2, func1, func0); and(i_jr, r_type,func5,func4, func3,func2,func1,func0); and(i_addi,op5,op4, op3,op2,op1,op0); and(i_andi,op5,op4, op3, op2,op1,op0); and(i_ori, op5,op4, op3, op2,op1, op0); and(i_xori,op5,op4, op3, op2, op1,op0); an

13、d(i_lw, op5,op4,op3,op2, op1, op0); and(i_sw, op5,op4, op3,op2, op1, op0); and(i_beq, op5,op4,op3, op2,op1, op0); and(i_bne, op5,op4,op3, op2,op1, op0); and(i_lui, op5,op4, op3, op2, op1, op0); and(i_j, op5,op4,op3,op2, op1,op0); and(i_jal, op5,op4,op3,op2, op1, op0);wire i_shift;or (i_shift,i_sll,i

14、_srl,i_sra);always * begin/ control signals dfault outputs:wpc =0;/ do not write pcwir =0;/ do not write irwmem= 0;/ do not write memorywreg =0;/ do not write register fileiord =0;/ select pc as memory addressaluc =4bx000;/ ALU operation: addalusrca =0;/ ALU input a: reg a or saalusrcb =2h0;/ ALU in

15、put b: reg bregrt =0;/ reg dest no: rdm2reg= 0;/ select reg cshift =0;/ select reg apcsource =2h0;/ select alu outputjal = 0;/ not a jalsext= 1;/ sign extendcase (state)/- IF:sif: begin/ IF statewpc =1;/ write pcwir =1;/ write IRalusrca =1;/ PCalusrcb =2h1;/ 4next_state =sid;/ next state: IDend/- ID

16、:sid:begin/ ID stateif (i_j) begin/ j instructionpcsource= 2h3;/ jump addresswpc= 1;/ write PCnext_state= sif;/ next state: IFendelse if (i_jal) begin/ jal instructionpcsource= 2h3;/ jump addresswpc= 1;/ write PCjal= 1;/ reg no = 31wreg= 1;/ save PC+4next_state= sif;/ next state: IFendelse if (i_jr)

17、 begin/ jr instructionpcsource= 2h2;/ jump registerwpc= 1;/ write PCnext_state= sif;/ next state: IFendelse begin/ other instructionaluc= 4bx000;/ addalusrca= 1;/ PCalusrcb= 2h3;/ branch offsetnext_state= sexe;/ next state: EXEendend/ EXE:sexe: begin / EXE statealuc3 = i_sra;aluc2 = i_sub | i_or | i

18、_srl | i_sra | i_ori | i_lui ;aluc1i_xor | i_sll | i_srl | i_sra | i_xori | i_beq | i_bne |i_lui ;| i_srl | i_sra | i_andi | i_ori ; / beq or bne instruction / branch address/ next state: IF/ other instruction/ lw or sw instruction/ select offset/ next state: MEM/ other instruction/ shift instructio

19、naluc0 = i_and | i_or | i_sllif (i_beq | i_bne) beginpcsource = 2h1;wpc = i_beq & z | i_bne & z; / write PC next_state = sif;endelse beginif(i_lw | i_sw) beginalusrcb = 2h2;next_state = smem;endelse beginif (i_shift)shift = 1;if (i_addi | i_andi | i_ori | i_xori | i_lui)alusrcb =2h2;/ select immedia

20、teif (i_andi | i_ori |i_xori)sext =0;/ 0-extendnext_state =swb;/ next state: WBend end end/ MEM:smem: begin / MEM stateiord = 1; / memory address = Cif (i_lw) beginnext_state = swb; / next state: WBendelse begin / store wmem = 1; / write memory next_state = sif; / next state: IFendend/ WB:swb: begin

21、 / WB stateif (i_lw)m2reg = 1; / select memory dataif (i_lw | i_addi | i_andi | i_ori | i_xori | i_lui)regrt = 1; / reg dest no: rtwreg = 1; / write register filenext_state = sif; / next state: IFend/ ENDdefault: begin next_state endendcaseend/ state registersalways (posedge clock or negedge resetn)

22、 begin if (resetn = 0) begin state = sif;endelse beginstate = next_state;endendendmodule32 位带使能端触发器： module dffe32 (d,clk,clrn,e,q);input 31:0 d;input clk,clrn,e;output 31:0 q;reg 31:0 q;always (negedge clrn or posedge clk)if (clrn = 0) beginq = 0;endelse beginif(e = 1) q = d;endendmodule32 位触发器：mod

23、ule dff32 (d,clk,clrn,q);input 31:0 d;input clk,clrn;output 31:0 q;reg 31:0 q;always (negedge clrn or posedge clk)if (clrn = 0) beginq = 0;end else begin q = d;endendmoduleALU 计算部件： module alu (a,b,aluc,r,z);input 31:0 a,b; input 3:0 aluc; output 31:0 r; output z;assign r = cal(a,b,aluc);assign z =

24、|r; function 31:0 cal;input 31:0 a,b;input 3:0 aluc;casex (aluc)4bx000: cal=a+b; 4bx100: cal=a-b; 4bx001: cal=a&b; 4bx101: cal=a|b; 4bx010: cal=ab; 4bx110: cal=b15:0,16h0; 4bx011: cal=ba4:0;4b1111: cal=$signed(b)a4:0;endcaseendfunction endmodule其他部件： module f (reg_dest,jal,wn);input4:0reg_dest;input

25、jal;output4:0wn;assignwn =reg_dest | 5jal;endmodulemodule sa (di,dot); input 4:0 di; output 31:0 dot; assign dot = 27b0,di;endmodulemodule out4 (out); output 31:0 out; assign out = 32h4;endmodulemodule e (immin,sext,immediate,offset);input15:0immin;inputsext;output31:0immediate,offset;wiree =sext &

26、immin15;wire15:0imm =16e;assignoffset =imm13:0,immin15:0,1b0,1b0;assignimmediate =imm,immin15:0;endmodulemodule combine (address,pc,add);input25:0address;input3:0pc;output31:0add;assignadd =pc3:0,address25:0,1b0,1b0;endmodulemodule convert1 (dain,sain,op,func,rs,rt,rd,imm,addr);input31:0 dain;output4:0sain,rs,rt,rd;output5:0op,func;output15:0imm;output25:0addr;assignsain =dain10:6;assignop= dain31:26;assignfunc