EDA综合实验设计报告.docx

1、EDA综合实验设计报告 Beijing Jiaotong University EDA实验设计报告 TYP 电气0906 09291183实验1：熟悉QUARTUS II软件的使用通过下载及安装，可在电脑上运行AlteraQuartusII。打开软件，新建一个工程，在工程底下新建一个VHDL File，即可实现编程功能。编完程序后点击Start Compilation可试运行程序，待编写的程序运行无误后，再在此工程下新建一个Vector Waveform File，给程序中的输入变量赋值，保存后点击Start Simulation即可实现程序的仿真。实验2：组合电路设计1、设计一个四位的全加器

2、，进位输出是快速进位位。设计思路：为实现快速进位，我选取4个一位全加器同时运行，及通过元件例化语句component，将底层的设计实体定义为一个元件，使实体中包含4个低一级的元件，并与当前设计实体中的指定端口连接，从而实现快速进位。程序：其中实体名为SB1，Uo:SB port map(a0,b0,c1,s0,d)等语句即为定义低一级的1位全加器。具体程序如下：library ieee;use ieee.std_logic_1164.all;entity SB1 is port(a0,a1,a2,a3:in std_logic; b0,b1,b2,b3:in std_logic; c1:in

3、std_logic; s0,s1,s2,s3:out std_logic; c0:out std_logic);end SB1;architecture yi of SB1 is component SB port(a,b,c:in std_logic; s,co:out std_logic); end component; signal d,e,f:std_logic; begin Uo:SB port map(a0,b0,c1,s0,d); U1:SB port map(a1,b1,d,s1,e); U2:SB port map(a2,b2,e,s2,f); U3:SB port map(

4、a3,b3,f,s3,c0); end yi; library ieee;use ieee.std_logic_1164.all;entity SB is port(a,b,c:in std_logic; s,co:out std_logic);end SB; architecture yi of SB is begin s=a xor b xor c; co outt(15 downto 0) outt(15 downto 0) outt(15 downto 0) outt(15 downto 0) outt(15 downto 0) outt(15 downto 0) outt(15 do

5、wnto 0) outt(15 downto 0) outt(15 downto 0) outt(15 downto 0) outt(15 downto 0) outt(15 downto 0) outt(15 downto 0) outt(15 downto 0) outt(15 downto 0) outt(15 downto 0) outt(15 downto 0)outt(15 downto 0)=1111111111111111;end case;end if;end process;end architecture;仿真波形： 当输入inn为1010时，输出outt中的第10个端口

6、变为低电平，即实现了译码的功能。实际仿真波形如下图。实验3：时序电路设计设计4位二进制同步加/减法可逆计数器，其中输入:clr: 异步清零(高电平有效) clk: 时钟输入 d3-d0: 4位二进制数输入端updown： 加/减法控制信号（1加，0减）输出:q3-q0: 4位二进制计数输出co: 进位输出bo: 借位输出设计思路：用if语句实现清零及加减法的选择。若选择updown=1，则当时钟输入为高电平时输入的d就加1，当d=1111时进位输出co就变1，最后将d中的数送给q来输出，以达到4位二进制同步加/减法可逆计数器的设计。程序： 其中实体名为SB3，程序中两个关键的if语句即可实现加

7、减法的控制及进位、借位的输出。具体程序如下：library IEEE;use IEEE.std_logic_1164.all;use IEEE.std_logic_unsigned.all;entity SB3 is port(clk:in STD_LOGIC; updown:in STD_LOGIC; clr:in STD_LOGIC; q:out STD_LOGIC_VECTOR (3 downto 0); co,bo:out std_logic);end SB3;architecture sbb of SB3 issignal d:std_logic_vector(3 downto 0)

8、;beginprocess(clk,clr,updown)begin if clr=1 then d=0000; elsif clkevent and clk=1 then if updown=1 then d=d+1; co=0; bo=0; else d=d-1; co=0; bo=0; end if; if d=1111 and updown=1 then co=1; bo=0; end if; if d=0000 and updown=0 then bo=1; co=0; end if; end if;end process;process(d)begin qtmp0=1;tmp1=0

9、;tmp2 case div is when 00= case cnt0 is when 0=tmp0=0;tmp1=1;tmp2tmp0=0;tmp1=1;tmp2tmp0=0;tmp1=0;tmp2tmp0=1;tmp1=0;tmp2tmp0=1;tmp1=0;tmp2tmp0=1;tmp1=1;tmp2=0; cnt0=0; 以上程序即可输出占空比1：1，6分频，三路互差120的信号。具体程序如下：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_arith.all;use ieee.std_logic_unsigne

10、d.all;entity SB4 is port ( clk, reset:in std_logic; div:in std_logic_vector(1 downto 0); ctrl:in std_logic_vector(1 downto 0); outa,outb,outc:out std_logic);end SB4;architecture SB of SB4 issignal tmp0:std_logic; signal tmp1:std_logic; signal tmp2:std_logic; signal cnt0:integer range 0 to 5:=0; sign

11、al cnt1:integer range 0 to 11:=0; signal cnt2:integer range 0 to 17:=0; signal cnt3:integer range 0 to 23:=0; begin process(clk,reset,div,ctrl) begin if clkevent and clk=1 then if reset=0 then cnt0=0; cnt1=0; cnt2=0; cnt3=0; tmp0=0; tmp1=0; tmp2=0; elsif reset=1 then cnt0=cnt0+1; cnt1=cnt1+1; cnt2=c

12、nt2+1; cnt3 case div is when 00= case cnt0 is when 0=tmp0=0;tmp1=1;tmp2tmp0=0;tmp1=1;tmp2tmp0=0;tmp1=0;tmp2tmp0=1;tmp1=0;tmp2tmp0=1;tmp1=0;tmp2tmp0=1;tmp1=1;tmp2=0; cnt0 case cnt1 is when 0=tmp0=0;tmp1=1;tmp2tmp0=0;tmp1=1;tmp2tmp0=0;tmp1=1;tmp2tmp0=0;tmp1=1;tmp2tmp0=0;tmp1=0;tmp2tmp0=0;tmp1=0;tmp2tm

13、p0=1;tmp1=0;tmp2tmp0=1;tmp1=0;tmp2tmp0=1;tmp1=0;tmp2tmp0=1;tmp1=0;tmp2tmp0=1;tmp1=1;tmp2tmp0=1;tmp1=1;tmp2=0; cnt1 case cnt2 is when 0=tmp0=0;tmp1=1;tmp2tmp0=0;tmp1=1;tmp2tmp0=0;tmp1=1;tmp2tmp0=0;tmp1=1;tmp2tmp0=0;tmp1=1;tmp2tmp0=0;tmp1=1;tmp2tmp0=0;tmp1=0;tmp2tmp0=0;tmp1=0;tmp2tmp0=0;tmp1=0;tmp2tmp

14、0=1;tmp1=0;tmp2tmp0=1;tmp1=0;tmp2tmp0=1;tmp1=0;tmp2tmp0=1;tmp1=0;tmp2tmp0=1;tmp1=0;tmp2tmp0=1;tmp1=0;tmp2tmp0=1;tmp1=1;tmp2tmp0=1;tmp1=1;tmp2tmp0=1;tmp1=1;tmp2=0; cnt2 case cnt3 is when 0=tmp0=0;tmp1=1;tmp2tmp0=0;tmp1=1;tmp2tmp0=0;tmp1=1;tmp2tmp0=0;tmp1=1;tmp2tmp0=0;tmp1=1;tmp2tmp0=0;tmp1=1;tmp2tmp0

15、=0;tmp1=1;tmp2tmp0=0;tmp1=1;tmp2tmp0=0;tmp1=0;tmp2tmp0=0;tmp1=0;tmp2tmp0=0;tmp1=0;tmp2tmp0=0;tmp1=0;tmp2tmp0=1;tmp1=0;tmp2tmp0=1;tmp1=0;tmp2tmp0=1;tmp1=0;tmp2tmp0=1;tmp1=0;tmp2tmp0=1;tmp1=0;tmp2tmp0=1;tmp1=0;tmp2tmp0=1;tmp1=0;tmp2tmp0=1;tmp1=0;tmp2tmp0=1;tmp1=1;tmp2tmp0=1;tmp1=1;tmp2tmp0=1;tmp1=1;tm

16、p2tmp0=1;tmp1=1;tmp2=0; cnt3 case div is when 00= case cnt0 is when 0=tmp0=0;tmp1=1;tmp2tmp0=0;tmp1=1;tmp2tmp0=0;tmp1=0;tmp2tmp0=0;tmp1=0;tmp2tmp0=1;tmp1=0;tmp2tmp0=1;tmp1=0;tmp2=0; cnt0 case cnt1 is when 0=tmp0=0;tmp1=1;tmp2tmp0=0;tmp1=1;tmp2tmp0=0;tmp1=1;tmp2tmp0=0;tmp1=1;tmp2tmp0=0;tmp1=0;tmp2tmp0=0;tmp1=0;tmp2tmp0=0;tmp1=0;tmp2tmp0=0;tmp1=0;tmp2tmp0=1;tmp1=0;tmp2tmp0=1;tmp1=0;tmp2tmp0=1;tmp1=0;tmp2tmp0=1;tmp1