计算机组织与结构英文版课后答案.docx

1、计算机组织与结构英文版课后答案Solutions ManualCOMPUTER ORGANIZATION AND ARCHITECTUREDesigning for PerformanceSeventh EditionWilliam StallingsCopyright 2005: William Stallings 2005 by William StallingsAll rights reserved. No part of this document may be reproduced, in any form or by any means, or posted on the Inte

2、rnet, without permission in writing from the author.NoticeThis manual contains solutions to all of the review questions and homework problems in Computer Organization and Architecture, Seventh Edition. If you spot an error in a solution or in the wording of a problem, I would greatly appreciate it i

3、f you would forward the information via email to ws. An errata sheet for this manual, if needed, is available at WilliamSW.S.TABLE OF CONTENTSChapter 2: Computer Evolution and Performance 5Chapter 3: Computer Function and Interconnection 9Chapter 4: Cache Memory 14Chapter 5: Internal Memory 27Chapte

4、r 6: External Memory 33Chapter 7: Input/Output 37Chapter 8: Operating System Support 43Chapter 9: Computer Arithmetic 48Chapter 10: Instruction Sets: Characteristics and Functions 61Chapter 11: Instruction Sets: Addressing Modes and Formats 72Chapter 12: Processor Structure and Function 77Chapter 13

5、: Reduced Instruction Set Computers (RISCs) 83Chapter 14: Instruction-Level Parallelism and Superscalar Processors 87Chapter 15: The IA-64 Architecture 93Chapter 16: Control Unit Operation 97Chapter 17: Microprogrammed Control 100Chapter 18: Parallel Processing 103Appendix A: Number Systems 112Appen

6、dix B: Digital Logic 113Chapter 2Computer Evolution and PerformanceAnswers to Questions2.1 In a stored program computer, programs are represented in a form suitable for storing in memory alongside the data. The computer gets its instructions by reading them from memory, and a program can be set or a

7、ltered by setting the values of a portion of memory.2.2 A main memory, which stores both data and instructions: an arithmetic and logic unit (ALU) capable of operating on binary data; a control unit, which interprets the instructions in memory and causes them to be executed; and input and output (I/

8、O) equipment operated by the control unit.2.3 Gates, memory cells, and interconnections among gates and memory cells.2.4 Moore observed that the number of transistors that could be put on a single chip was doubling every year and correctly predicted that this pace would continue into the near future

9、.2.5 Similar or identical instruction set: In many cases, the same set of machine instructions is supported on all members of the family. Thus, a program that executes on one machine will also execute on any other. Similar or identical operating system: The same basic operating system is available f

10、or all family members. Increasing speed: The rate of instruction execution increases in going from lower to higher family members. Increasing Number of I/O ports: In going from lower to higher family members. Increasing memory size: In going from lower to higher family members. Increasing cost: In g

11、oing from lower to higher family members.2.6 In a microprocessor, all of the components of the CPU are on a single chip.Answers to Problems2.1 This program is developed in HAYE98. The vectors A, B, and C are each stored in 1,000 contiguous locations in memory, beginning at locations 1001, 2001, and

12、3001, respectively. The program begins with the left half of location 3. A counting variable N is set to 999 and decremented after each step until it reaches 1. Thus, the vectors are processed from high location to low location.LocationInstructionComments0999Constant (count N)11Constant21000Constant

13、3LLOAD M(2000)Transfer A(I) to AC3RADD M(3000)Compute A(I) + B(I)4LSTOR M(4000)Transfer sum to C(I)4RLOAD M(0)Load count N5LSUB M(1)Decrement N by 15RJUMP+ M(6, 20:39)Test N and branch to 6R if nonnegative6LJUMP M(6, 0:19)Halt6RSTOR M(0)Update N7LADD M(1)Increment AC by 17RADD M(2)8LSTOR M(3, 8:19)M

14、odify address in 3L8RADD M(2)9LSTOR M(3, 28:39)Modify address in 3R9RADD M(2)10LSTOR M(4, 8:19)Modify address in 4L10RJUMP M(3, 0:19)Branch to 3L2.2 a.OpcodeOperand00000001000000000010 b. First, the CPU must make access memory to fetch the instruction. The instruction contains the address of the dat

15、a we want to load. During the execute phase accesses memory to load the data value located at that address for a total of two trips to memory.2.3 To read a value from memory, the CPU puts the address of the value it wants into the MAR. The CPU then asserts the Read control line to memory and places

16、the address on the address bus. Memory places the contents of the memory location passed on the data bus. This data is then transferred to the MBR. To write a value to memory, the CPU puts the address of the value it wants to write into the MAR. The CPU also places the data it wants to write into th

17、e MBR. The CPU then asserts the Write control line to memory and places the address on the address bus and the data on the data bus. Memory transfers the data on the data bus into the corresponding memory location.2.4AddressContents08A 08B 08C08DLOAD M(0FA)STOR M(0FB)LOAD M(0FA)JUMP +M(08D)LOAD M(0F

18、A)STOR M(0FB) This program will store the absolute value of content at memory location 0FA into memory location 0FB.2.5 All data paths to/from MBR are 40 bits. All data paths to/from MAR are 12 bits. Paths to/from AC are 40 bits. Paths to/from MQ are 40 bits.2.6 The purpose is to increase performanc

19、e. When an address is presented to a memory module, there is some time delay before the read or write operation can be performed. While this is happening, an address can be presented to the other module. For a series of requests for successive words, the maximum rate is doubled. 2.7 The discrepancy

20、can be explained by noting that other system components aside from clock speed make a big difference in overall system speed. In particular, memory systems and advances in I/O processing contribute to the performance ratio. A system is only as fast as its slowest link. In recent years, the bottlenec

21、ks have been the performance of memory modules and bus speed.2.8 As noted in the answer to Problem 2.7, even though the Intel machine may have a faster clock speed (2.4 GHz vs. 1.2 GHz), that does not necessarily mean the system will perform faster. Different systems are not comparable on clock spee

22、d. Other factors such as the system components (memory, buses, architecture) and the instruction sets must also be taken into account. A more accurate measure is to run both systems on a benchmark. Benchmark programs exist for certain tasks, such as running office applications, performing floating p

23、oint operations, graphics operations, and so on. The systems can be compared to each other on how long they take to complete these tasks. According to Apple Computer, the G4 is comparable or better than a higher-clock speed Pentium on many benchmarks.2.9 This representation is wasteful because to re

24、present a single decimal digit from 0 through 9 we need to have ten tubes. If we could have an arbitrary number of these tubes ON at the same time, then those same tubes could be treated as binary bits. With ten bits, we can represent 210 patterns, or 1024 patterns. For integers, these patterns coul

25、d be used to represent the numbers from 0 through 1023.2.10 IcpmkInstruction set architectureXXCompiler technologyXXXProcessor implementationXXCache and memory hierarchyXX Source: HWAN932.11 MIPS rate = f/(CPI 106)2.12 a. We can express the MIPs rate as: (MIPS rate)/106 = Ic/T. So that: Ic = T (MIPS

26、 rate)/106. The ratio of the instruction count of the RS/6000 to the VAX is x 18/12x 1 = 1.5. b. For the Vax, CPI = (5 MHz)/(1 MIPS) = 5. For the RS/6000, CPI = 25/18 = 1.39.2.13 CPI = 1.55; MIPS rate = 25.8; Execution time = 3.87 ns. Source: HWAN932.14 a. Ultimately, the user is concerned with the

27、execution time of a system, not its execution rate. If we take arithmetic mean of the MIPS rates of various benchmark programs, we get a result that is proportional to the sum of the inverses of execution times. But this is not inversely proportional to the sum of execution times. In other words, th

28、e arithmetic mean of the MIPS rate does not cleanly relate to execution time. On the other hand, the harmonic mean MIPS rate is the inverse of the average execution time. b. Arithmetic meanHarmonic MeanRankComputer A25.3 MIPS0.25 MIPS2Computer B2.8 MIPS0.21 MIPS3Computer C3.25 MIPS2.1 MIPS1hapter 3C

29、omputer Function and InterconnectionAnswers to Questions3.1 Processor-memory: Data may be transferred from processor to memory or from memory to processor. Processor-I/O: Data may be transferred to or from a peripheral device by transferring between the processor and an I/O module. Data processing:

30、The processor may perform some arithmetic or logic operation on data. Control: An instruction may specify that the sequence of execution be altered.3.2 Instruction address calculation (iac): Determine the address of the next instruction to be executed. Instruction fetch (if): Read instruction from i

31、ts memory location into the processor. Instruction operation decoding (iod): Analyze instruction to determine type of operation to be performed and operand(s) to be used. Operand address calculation (oac): If the operation involves reference to an operand in memory or available via I/O, then determine the address of the operand. Operand fetch (of): Fetch the operand from memory or read it in from I/O. Data operation (do): Perform the operation indicated in the instruction. Operand sto