锁相技术译文翻译数字混合PLL频率合成器的开关特性分析.docx

1、锁相技术译文翻译数字混合PLL频率合成器的开关特性分析锁相技术译文翻译英文原名： Analysis of Switching Characteristics of the Digital Hybrid PLL Frequency Synthesizer译文：数字混合PLL频率合成器的开关特性分析年纪专业：_姓名：_ 学号：_年 月 日英文中文Analysis of Switching Characteristics of the Digital Hybrid PLL Frequency SynthesizerHeung-Gyoon Ryu, Member, IEEE, and Hyun-Seo

2、k LeeAbstractIn this paper, we address the switching characteristics of the digital hybrid phase-locked loop (DH-PLL) frequency synthesizer. We analyze the effects of the division ratio for frequency synthesis and the component errors of a DH-PLL circuit on the switching performance. Gain variation,

3、 offset error generated in a digital-to-analog converter, and frequency drift error of voltage-controlled oscillation due to temperature and aging are considered as the errors of the circuit components. From the simulation results, the conventional charge-pump PLL system has much different switching

4、 time for the change spacing of the frequency synthesis. On the contrary, the variation of the switching time is not so great in the DH-PLL system when the error magnitude does not exceed the 4 least significant bit error. To guarantee the required minimum switching speed, it is important that the t

5、olerable error range be determined.Index TermsDevice error and switching, digital hybrid phase-locked loop (DH-PLL), frequency synthesizer.I. INTRODUCTIONHIGH-SPEED switching is one of the most important characteristics in frequency synthesizers. In 1999, Abou El-Ela proposed a method in which an ad

6、ditional input to a voltage control oscillator (VCO) is required to get higher switching speed in a phase-locked loop (PLL) frequency synthesizer 1. This is a structure to provide VCO with an additional input of the sawtooth wave using a digital-to-analog (D/A) converter. Whenever frequency is synth

7、esized, the waveform generator with the most optimum slope and duration is required. Therefore, the complicated design and the exact synchronization for high-speed switching make it disadvantageous.In 1995, Materna addressed the PLL structure based on a pre-tuning approach that uses an external tuni

8、ng voltage to a VCO by a D/A converter for extremely high-frequency satellite applications 2. However, there was no discussion about the system switching characteristics. In 2001, Ryu proposed a simplified structure that improves switching speed and power consumption of the digital direct-frequency

9、synthesizer (DDFS)-driven PLL 3. Although there is an advantage of the effective wide-band applications, the operating speed of the whole system depends on PLL speed. In 2000, Fouzar proposed a PLL frequency synthesizer that has dual-loop form using a frequency-to-voltage converter (FVC) 4. High swi

10、tching speed can be obtained by use of the FVC and the coarse tuning controller using the output of the phase detector and VCO. Additional hardware complexity is cumbersome and FVC limits the switching speed.In this paper, the switching performance characteristics of the digital hybrid (DH)-PLL freq

11、uency synthesizer based on pretuning approach is addressed. The effects of the division ratio for frequency synthesis and errors of circuit components on the switching performance of the DH-PLL are newly analyzed and presented with simulation results. Gain variation, offset error generated in a D/A

12、converter, and frequency drift error of VCO due to temperature and aging can be included in the errors of the circuit components. D/A converters of 10-, 12-, and 14-bit word length are considered in the paper.II. DH-PLL FREQUENCY SYNTHESIZER Fig. 1 shows a block diagram of a digital hybrid PLL. The

13、VCO is controlled by a composite signal of both loop filter output and D/A converter output. DH-PLL is a hybrid structure of the conventional closed-loop charge-pump PLL and open-loop VCO control, which is made up of the digital lookup table, D/A converter, and VCO. The digital lookup table with the

14、 information about the voltage-frequency characteristic of VCO rapidly leads the steady-state voltage by the D/A converter output. A frequency control word goes into the programmable counter and lookup table at the same time. In this DH-PLL, the loop filter as shown in Fig. 2 is used since the conve

15、ntional closed-loop is the type II charge-pump PLL system 5, 6, 9.At first, C1 and R1 are considered for a second-order PLL system design to meet the desired specifications without C2.Next, to reduce the ripple of the steady-state response, a small C2 is added that is much smaller than C1 and has li

16、ttle effect on the loop dynamics. So, in this case, the PLL natural frequency (n ) and the damping factor () are given by 6, 7Where Kpd is the combined transfer gain of the phase-frequency detector and charge-pump, Kvco is the VCO gain factor, and N is the division ratio. The damping factor is selec

17、ted in the first place and can be obtained by (2). Damping factor () has to be bigger than the common value used in the conventional design for the smooth transient response in frequency hopping process. The reason can be explained as follows. It is true that a smooth transient response reduces the

18、switching speed in the conventional PLL system. In the DH-PLL system, however, the smoothness is important and enhances the accuracy and stability of output frequency in steady state at very little sacrifice of the switching time, since the high-speed switching characteristic is already guaranteed i

19、n pretune structure. So it ranges from 1.0 to 1.5. Next, the C2 of the loop filter is used for the ripple control and transient response of VCO control voltage. C2 is C1/, where is constant. If is small, VCO control voltage has a small ripple that also produces small jitter, but the transient respon

20、se becomes slow. On the other hand, large leads to fast transient response but a large ripple, which makes the output jitter increase. Since the smoothness, fast transient response, and smaller ripple of VCO control voltage are simultaneously considered in this paper, simulation results show that it

21、 is proper to select =10.Then, the closed-loop PLL can be approximated to the second-order system, since C2 has little effect on the loop dynamics 8.Fig. 3. Switching responses of VCO control voltage (=1 and =10). (a) PLL (15.0 - 15.1 MHz); (b) DH-PLL (15.0 - 15.1 MHz). (c) PLL (15.0 - 30.0 MHz); (d

22、) DH-PLL (15.0 - 30.0 MHz).Fig. 4. Error effects of D/A converter and VCO.Fig. 5. Mathematical models of device errors.III. ANALYSIS OF SWITCHING CHARACTERISTICSA. Division Ratio The switching time and output jitter characteristic of the frequency synthesizer depend on the frequency division ratio.

23、Damping factor is 1.0 for both conventional PLL and DH-PLL. Parameterization of loop filter in Fig. 2 is based on the second-order PLL system. Input reference frequency is 100 kHz, phase detector gain （Kpd）is 1 mA/2, VCO gain （Kvco）is 5 MHz/V, and output frequency bandwidth is 1530 MHz. Frequency sy

24、nthesis spacing is divided into two groups: narrow hopping (from 15.0 to 15.1 MHz) and wide hopping (from 15.0 to 30.0 MHz). Settling time is defined as the required time that the response ripple is reduced into less than 1% of frequency hop spacing by division ratio. The performance analysis result

25、s are shown in Table I. Ripple voltage is measured in steady state of VCO control voltage. In the case of narrow hop spacing, DH-PLL is about 5.84 times faster than the conventional PLL, as shown in Fig. 3(a), (b). In the case of wide hop spacing, the DH-PLL is 31.68 times faster than the convention

26、al system. There is a 7.26 times difference in switching speed between narrow hopping and wide hopping of the conventional PLL. On the contrary, DH-PLL has a small gap of 1.34 times in the same condition. Therefore, there is no great switching performance variation according to frequency hop spacing

27、 in DH-PLL. As shown in Table I, the VCO control voltage ripple of the DH-PLL system is not greatly different from the ripple of the conventional PLL system when is ten. Also, if the DH-PLL system is a third-order system in the case of =5, we get the lower ripple in the steady state by the simulatio

28、n at very little sacrifice of switching time. In the case of a type-I PLL system that is not charge-pumped PLL, the transient response of the third-order PLL system could be even faster than that of the second-order system 10. However, the third-order system generally exhibits slower transient respo

29、nse than the second-order system in the case of a type-II charge-pumped PLL system, as in this paper 9.Fig. 6. Switching responses versus several D/A converter word (W) errors. (a) Conventional PLL: 15.0 - 18.0 MHz. (b) DH-PLL: No error case of W = 153, 15.0 - 18.0 MHz. (c) DH-PLL: No error case of

30、W = 153, 15.0 - 18.0 MHz. (d) In case of W = 155, +2 LSB error. (e) In case of W =149, -4 LSB error.B. Device Errors In the DH-PLL architecture, a D/A converter outputs an analog control voltage to which VCO will be settled. There may be the problem that the D/A converter can produce an undesired ou

31、tput voltage by an unexpected error. It may be gain error and offset error of the D/A converter due to the temperature variation and device aging. In addition, the characteristic curve of VCO may be moved to generate frequency drift error because of the temperature and aging. This error may make a s

32、erious influence upon the synthesizer system. In the D/A part of Fig. 4, a is the ideal output of the D/A converter, b is the D/A converter output when offset error only exists, and c is the D/A converter output when both offset and gain error exist. In the VCO part, A is a desired output of VCO and B is output by c of the D/A part. C and D are output by c of the D/A part and frequency drift. Fig. 5 is a mathematical model of Fig. 4. The output voltage of the practical D/A converter beco