Practical 1Introduction to lab hardwaresoftware.docx

1、Practical 1Introduction to lab hardware softwarePractical 1: Introduction to Lab Hardware and SoftwareIntroductionThis Practical consists of an introduction to creating simple circuits on an FPGA using VHDL and Xilinx ISE. Firstly you will create a new project using the wizard of Xilinx ISE. This Pr

2、actical consists of several steps broken down over this document. In this Practical exercise, we will first learn how to create a simple VHDL project of a 2-to-1 multiplexer (MUX) using Xilinx ISE. After the design is fully verified, we will use Xilinx ISE to synthesize the design into a Spartan 3 F

3、PGA configuration data file which will then be downloaded onto a Spartan 3 printed circuit board (PCB) where the implemented design will be verified. You will secondly learn how to design and implement a few basic logic functions so as to be familiar with the Xilinx ISE design tool and basic VHDL. T

4、ask 1: 2-to-1 multiplexerThe 2-to-1 multiplexer has three inputs (two data inputs and one select input) and one data output as below: Data Inputs: Din0, Din1 Select Input: Sel Data Output: DoutIts Logic Function is: when Sel=0, Dout=Din0; when Sel=1, Dout=Din1. Its Boolean Logic Equation is: Dout =

5、Din0 * Sel + Din1 * /Sel. Follow the next steps to create, design and implement the above 2-to-1 multiplexer. Design StepsStep 1: Create a new project using ISE: Click the start menu, and type in Project. Then look for 64-bit Project Navigator and click on it. You may use other ways launch Xilinx IS

6、E. After ISE is launched, we will create a new project in File - New ProjectCreate a new project under the directory “C:Tem or another directory of your choice, and give the project a descriptive name such as Lab0 VHDL. We strongly reckon you save all your projects. Also set the “Top-level source ty

7、pe: to “HDL. Click “Next.The Spartan 3 Starter Kit PCB board uses a Xilinx Spartan3 XC3S200 FPGA chip which is packaged in a flat thin 256-pin (FT256) Ball Grid Array, so make the following changes. Click “Next when you are done.The next page displays a summary of the new project. Click “Finish when

8、 youre done to exit.Step 2: Create circuit using VHDL fileClick on Project - New Source.Select VHDL module and give the file a name and click “Next”.Add the port names and directions as shown.Click “Finish to exit the wizard.Add the following line of code:Dout New Source.Click Implementation Constra

9、ints File in the left frame and type in the name for the constraints file, for example mux21. Then click Next and Finish.Double click on the I/O Pin Planning (PlanAhead) - Post-Synthesis under Under Constraints to launch PlanAhead. Step 4: Implement Design Double click on “Implement Design ” to use

10、your constraintDouble-click on “Generate Programming File to generate FPGA configuration data file such as “21MUX.bit”.Step 5: Program FPGAConnect the 5V DC power cable to the power input on the demo board (J4).Connect the download JTAG-USB cable between the PC parallel port and the demo board (J7).

11、 Carefully note the position of the label on the cable.Start “Adept” Software, which can download the bit file onto the FPGA through JTAG-USB cable. You can either choose to program FPGA for PROM. Verify your implementation and show your result to the Tutor for marking when you are ready. Task 2: Im

12、plement the next basic logic functions following the same steps above. You need to define independent project for each of the functions below: AND Gate OR Gate NAND Gate Exclusive-NOR GateTask 3: Implement the next 74XX30 chip:Task 4: Use the K-MAP to simplify the Boolean function in product of sums, and implement the simplified logic, and verify it by comparing with the Truth Table. F(A, B, C, D) =