河工大 eda实验考试题目及答案.docx

1、河工大 eda实验考试题目及答案1,设计一个带计数使能、同步复位、带进位输出的增1六位二进制计数器，计数结果由共阴极七段数码管显示。library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity counter is port(clk,clk1,en,clr:in std_logic; ledout:out std_logic_vector(6 downto 0); scanout:out std_logic_vector(1 downto 0); co:out std_logic);end cou

2、nter;architecture a of counter issignal cnt:std_logic_vector(7 downto 0);signal led:std_logic_vector(6 downto 0);signal scan:std_logic:=0;signal hex:std_logic_vector(3 downto 0);begin process(clk) begin if(clkevent and clk=1)then if en=1then if clr=1then cnt0); else if cnt=00111111then cnt=00000000;

3、 co=1; else cnt=cnt+1; co=0; end if; end if; end if; end if; end process;process(clk1) begin if clk1event and clk1=1then scan=not scan; end if;end process;ledout= not led;scanout=10 when scan=0 else 01;hex=cnt(7 downto 4) when scan=1else cnt(3 downto 0);with hex selectled=1111001when0001, 0100100whe

4、n0010, 0110000when0011, 0011001when0100, 0010010when0101, 0000010when0110, 1111000when0111, 0000000when1000, 0010000when1001, 0001000when1010, 0000011when1011, 1000110when1100, 0100001when1101, 0000110when1110, 0001110when1111, 1000000when others;end a;2、设计一个带计数使能、异步复位、带进位输出的增1二十进制计数器，计数结果由共阴极七段数码管显

5、示。library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity da is Port ( clk : in STD_LOGIC; clk1 : in STD_LOGIC; clr : in STD_LOGIC; en : in STD_LOGIC; co : out STD_LOGIC; ledout : out STD_LOGIC_VECTOR (6 downto 0); sel : out STD_LOGIC_VECTOR (1 downto 0);end da;architecture e

6、havioral of da is signal cnt:std_logic_vector(7 downto 0):=00000000; signal led:std_logic_vector(6 downto 0); signal scan:std_logic:=0; signal hex:std_logic_vector(3 downto 0);begin process(clk,clr) begin if clr=1then cnt0); elsif clkevent and clk=1 then if en=1then if cnt=00001001then cnt=00010000;

7、 co=0; elsif cnt=00011001then cnt=00000000; co=1; else cnt=cnt+1; co=0; end if; end if; end if; end process; process(clk1) begin if clk1event and clk1=1then scan=not scan; end if; end process; hex=cnt(7 downto 4) when scan=1else cnt(3 downto 0); with hex select led=1111001when0001, 0100100when0010,

8、0110000when0011, 0011001when0100, 0010010when0101, 0000010when0110, 1111000when0111, 0000000when1000, 0010000when1001, 1000000when0000, 1111111when others; ledout= not led; sel=10 when scan=0 else 01;end ehavioral;3、设计一个带计数使能、同步复位、同步装载的可逆七位二进制计数器，计数结果由共阴极七段数码管显示。library ieee;use ieee.std_logic_1164.

9、all;use ieee.std_logic_unsigned.all;entity counter is port(clk,clks,clr,en,stld,dir:in std_logic; din:in std_logic_vector(6 downto 0); ledout:out std_logic_vector(6 downto 0);scanout:out std_logic_wector(1 downto 0); end counter; architecture a of counter is signal cnt:std_logic_vector(6 downto 0);

10、signal led:std_logic_vector(6 downto 0); signal scan:std_logic; signal hex:std_logic_vector(3 downto 0); begin process(clk,clr) beginif clkevent and clk=1thenif clr=1 thencnt0);elseif stld=0 thencnt=din;elsif en=1 thenif dir=1 then if cnt =”01111111” then cnt = “00000000”;co=1; else cnt = cnt + 1;en

11、d if; else if cnt =”00000000” then cnt = “01111111”;co=1; else cnt = cnt - 1;end if;end if;end if;end if;End if;end process;process(clks) begin if clksevent and clks=1then scan=not scan; end if; end process; ledout=not led; scanout=10 when scan=0 else 01; hex=0&cnt(6 downto 4) when scan=1 else cnt(3

12、 downto 0); with hex select led= 1111001when 0001, 0100100when 0010, 0110000when 0011, 0011001when 0100, 0010010when 0101, 0000010when 0110, 1111000when 0111, 0000000when 1000, 0010000when 1001, 0001000when 1010, 0000011when 1011, 1000110when 1100, 0100001when 1101, 0000110when 1110, 0001110when 111

13、1, 1000000when others; End a ;4、设计一个带计数使能、异步复位、异步装载、可逆计数的通用计数器。计数结果由共阴极七段数码管显示。library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity counter is generic(count_value:integer:=9); port(clk,clr,en,load,dir:in std_logic; data_in:in integer range 0 to count_value; count:out integ

14、er range 0 to count_value; ledout:out std_logic_vector(6 downto 0); end counter; architecture a of counter is signal cnt:integer range 0 to count_value; signal led:std_logic_vector(6 downto 0); begin process(load,clk)begin if clr=1 then cnt=0; elseif load=1 then cnt=data_in; elsif(clkevent and clk=1

15、) then if en=1 then if dir=1 then if cnt=count_value then cnt=0; else cnt=cnt+1; end if; else if cnt=0 then cnt=count_value; else cnt=cnt-1; end if; end if; end if; end if; end if;end process;count=cnt;ledout=not led;with cnt selectled= 1111001when 1, 0100100when 2, 0110000when 3, 0011001when 4, 001

16、0010when 5, 0000010when 6, 1111000when 7, 0000000when 8, 0010000when 9, 1000000when 0, 1111111when others;End a;5、设计一个具有16分频、8分频、4分频和2分频功能的分频器library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_arith.all;use ieee.std_logic_unsigned.all;entity clkdiv isport(clk:in std_logic;clk_div2:out std_l

17、ogic;clk_div4:out std_logic;clk_div8:out std_logic;clk_div16:out std_logic);end clkdiv;architecture rtl of clkdiv issignal count:std_logic_vector(3 downto 0);beginprocess(clk)beginif (clkevent and clk=1) thenif(count=1111 )then count0);elsecount=count+1;end if;end if;end process;clk_div2=count(0);cl

18、k_div4=count(1);clk_div8=count(2);clk_div16=count(3);end rtl;6、设计一个正负脉宽相等的通用分频器LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY counter ISGENERIC( count_value: INTEGER:=15); PORT (clk,clr,en: IN STD_LOGIC; count:OUT STD_LOGIC);END counter; ARCHITECTURE a OF counter ISS

19、IGNAL cnt: INTEGER RANGE 0 TO count_value;SIGNAL co: STD_LOGIC;SIGNAL count1:STD_LOGIC;BEGINPROCESS (clk,clr) BEGIN IF clr = 1 THEN cnt = 0; ELSIF (clkEVENT AND clk = 1) THEN IF en = 1 THEN IF cnt = count_value THEN cnt = 0; co=1; ELSE cnt = cnt + 1; co=0; END IF; END IF; END IF; END PROCESS;PROCESS

20、(co ) BEGIN IF( coEVENT AND co = 1)THEN count1=NOT count1; END IF; count=count1;END PROCESS;END a;7、设计一个正负脉宽可控的16分频的分频器library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity fen_pin isport(clk:in std_logic; din:in std_logic_vector(1 downto 0); count:out std_logic);end fen_pi

21、n;architecture behave of fen_pin issignal co:std_logic;begincount=co;process(clk)variable cnt:std_logic_vector(3 downto 0);beginif(clkevent and clk=1)thenif(cnt= 1111) thencnt:=0000;co=not co;elsif(cnt=din)thenco=1000)then cnt:=0000; else cnt:=cnt+1; end if; cout=1010)then cnt:=0000; cout=1; else cn

22、t:=cnt+1; cout=1110)then cnt:=0000;cout=1; else cnt:=cnt+1;cout=1111)then cnt:=0000; else cnt:=cnt+1; end if; cout=cnt(3); end if;end if;end process; ledout=not led; with en select led=0000000when00, 0001000when01, 0001110when10, 1000000when11, 1111111when others;end dgnfenpin;9、设计一个M序列发生器，M序列为“1110

23、0111”LIBRARY IEEE;USE IEEE.STD_logic_1164.all;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY SEQ IS PORT(CLK:IN STD_logic; FOUT:OUT STD_logic);END SEQ;ARCHITECTURE BEHAVE OF SEQ ISSIGNAL CNT:STD_logic_VECTOR(2 DOWNTO 0);BEGINPROCESS(CLK)BEGINIF CLKEVENT AND CLK=1 THENIF CNT=111 THENCNT=000;ELSECNT=CNT+1;END

24、 IF;END IF;END PROCESS;WITH CNT SELECTFOUT=1 WHEN 000,1 WHEN 001,1 WHEN 010,0 WHEN 011,0 WHEN 100,1 WHEN 101,1 WHEN 110,1 when 111,0 WHEN OTHERS;end BEHAVE;10、设计一个彩灯控制器，彩灯共有21个，每次顺序点亮相邻的3个彩灯，如此循环执行，循环的方向可以控制library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity caideng ispor

25、t(clk,reset:in std_logic; l_r:in std_logic; -控制循环方向； output:out std_logic_vector(15 downto 0);-输出end entity;architecture art of caideng issignal q:std_logic_vector(15 downto 0);beginprocess(clk,reset,l_r,q)begin if reset=1 then q=0000000000000000; elsif clkevent and clk=1 then if l_r=1 then -表示向右循环； if q=0000000000000000 then q=1110000000000000; else q=q(0)&q(15 downto 1); end if; else -向左循环; if q=0000000000000000 then q=0000000000000111; else q=q(14 downto 0)&q(15); end if; end if; end if; output=q;end process;end art;11、设计一个具有左移、右移控制，同步并行装载和串行装载的8位串行移位寄存器library