EDA程序设计试题及答案docx.docx
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EDA程序设计试题及答案docx
1・请画出下段程序的真值表,并说明该电路的功能。
LIBRARYieee;
USEieee.std_logic_1164.all;
ENTITYaaaIS
P0RT(oe,dir:
INSTD_LOGIC;
a,b:
INOUTSTD_LOGIC_VECTOR(7DOWNTO0);
ENDaaa;
ARCHITECTUREarOFaaaIS
BEGIN
输出
x3
x2
xl
xO
0
0
0
1
0
0
1
0
0
1
0
0
1
0
0
0
PROCESS(oe,dir)输入
BEGINalaO
IFoe=,0,THENav二"zzzzzzzz'';b<二"zzzzzzzz'';00
ELSIFoe=,l,THEN01
IFdir二'O'THENb<=a;10
ELSIFdir二TTHENa<=b;11
ENDIF;
ENDIF;
ENDPROCESS;
ENDar;
功能为:
2—4译码器4分
2.请说明下段程序的功能,写出真值表,并画出输入输出波形。
LIBRARYieee;
USEieee.std_logic_1164.all;
USEieee.std_logic_arith.all;
USEieee.std_logic_unsigned.all;
ENTITYaaaIS
PORT(reset,elk:
INSTD_LOGIC;
q:
BUFFERSTD_LOGIC_VECTOR(2DOWNTO0)
);
ENDaaa;
ARCHITECTUREbdOFaaaIS
BEGIN
PROCESS(clk,reset)
BEGIN
IF(wset='0‘)THENq<=n000H;
ELSIF(clk'eventANDclk=T)THEN
IF(q=5)THENq<=',000,';
ELSEq<=q+l;
ENDIF;
ENDIF;
ENDPROCESS;
ENDbd;
功能为:
带进位借位的4位加/减法器。
3分
输入输出波形图如下:
7分
b[3..O]
1.试用VHDL语言编程实现74LS273芯片的功能。
LIBRARYieee;
USE
ieee.std_logic_l164.ALL;
T
ENTITY
ls273
IS
V
PORT(
dr,
elk:
IN
std_logic;
d
IN
std_logic_vector(7DOWNTO0);
q
y
OUTstd_logic_vector(7DOWNTO0);
4'
END
丿,
ls273;
ARCHITECTURE
lock8
OF
ls273IS
1'
BEGIN
PROCESS(elk)r
BEGIN
IF(CLR=,0,)THENqCOOOOOOOO'';T
ELSEIF(clk?
eventANDelk二'1')THENq<=d;3'
ELSEIF(clk=,O,)THENqv二q;V
ENDIF;
ENDPROCESS;
ENDlock&3.请用VHDL语言编程实现一个状态向量发生器。
LIBRARYieee;
USE
ieee.std_logic_l164.ALL;
T
ENTITY
stas
IS
r
PORT(
cp,rst:
IN
std_logic;
P:
y
BUFFERstd_logic_vector(7DOWNTO0);
T
END
stas;
丿,
ARCHITECTURE
arstas
OFstasIS
V
BEGIN
PROCESS(cp)
BEGIN
IF(rst=,,0,?
)THENpv=”0000000(F;V
ELSEIF(cp9eventANDcp二'1')V
WITHpSELECT
p<=^^10101010^^
WHEN
“00000000";
”01010101"
WHEN
T0101010";
5001111”
WHEN
“01010101”;
^^11110000^^
WHEN
“00001111':
”11111111”
WHEN
Til10000";
”00000000”
WHEN
“niiiiii”;
"00000000''
WHEN
OTHERS;
ENDIF
ENDPROCESS;
ENDarstas;
1•阅读下段程序,画出该电路的真值表,并详细说明该电路的功能。
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
USEIEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITYab_8IS
PORT(a,b:
INSTD_LOGIC_VECTOR(7DOWNTO0);
ahb,alb,aeb:
OUTSTD_LOGIC);
ENDab_8;
ARCHITECTUREbdOFab_8IS
BEGIN
PROCESS(a,b)
BEGIN
IFa>bTHENahbv二T;alb<=,0,;aeb<=,0,;
ELSIFaELSEahbv='O';albv二'O';aebv二T;
ENDIF;
ENDPROCESS;
ENDbd;
1.
(1)真值表如下:
(5J
输入
输出
a>b
ahb
alb
aeb
a>b
1
0
0
a
0
1
0
a=b
0
0
1
(2)该电路是一个8位两输入比较器,(20
a、b是两个8位输入端;(1‘)
ahb、alb和aeb为比较结果输岀端,某种比较结果为真时,相应的输出端为"1”,其余端输岀为“0”。
(25)
1.试用VHDL语言编程实现一个2-4译码器,其真表如下:
输入端
输出端
en
select
y
0
XX
Till”
1
00
Tiio”
1
01
T101"
1
10
T011"
1
11
“0111”
2-4译码器码参考程序如下:
(答案不唯一,用case语句、with...select语句都可以。
)
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;(1J
ENTITYym24IS
PORT(en:
INSTD_LOGIC;
select:
OUTSTD_LOGIC_VECTOR(1DOWNTO0);
y:
OUTSTD_LOGIC_VECTOR(3DOWNTO0)(3J
);
ENDym24;
ARCHITECTUREbdOFym24IS
BEGIN
PROCESS(en)(1J
IF(en=T)THEN
yv="]110',
WHEN
se8ct=W'
ELSE
,nor,
WHEN
select="01"
ELSE
WHEN
select二"IO"
ELSE
"Olli”
WHEN
select=''ll"
ELSE
(4')
ELSEy<=,,iiir,;
ENDPROCESS;
ENDbd;
2•试用VHDL语言设计一个六路8位总线复用器,
其中A、B、C、D、E、F都是8位输入总
线,Q为8位输出总线,S为3位选择端,其功能如下:
输入端
输出端
S2
SI
so
Q7~Q0
0
0
0
Q=A
0
0
1
Q=B
0
1
0
Q=C
0
1
1
Q二D
1
0
0
Q=E
1
0
1
Q=F
其它
B=“00000000”
六路8位总线复用器参考程序:
(答案不唯一)
LIBRARYieee;
USEieee.std_logic_l164.ALL;
ENTITYmux6IS(V)
PORT(S:
INstd_logic_vector(2DOWNTO0);
A,B,C,D,E,F:
INstd_logic_vector(7DOWNTO0);
Q:
OUTstd_logic_vector(7DOWNTO0)
);(3‘)
ENDmux6;
ARCHITECTUREbdOFmux6IS
BEGIN
PROCESS(S)
BEGIN(1J
CASESIS
WHENn000n=>Q<=A;
WHENn001H=>Q<=B;
WHENn010H=>Q<=C;
WHENn0Hn=>Q<=D;
WHENn100H=>Q<=E;
WHENn101H=>Q<=F;
WHENOTHERS=>Q<=HOOOOOOOOn;(4')
ENDCASE;
ENDPROCESS;
ENDbd;
2、已知三选一电路如图,判断下列程序是否有错误,如有则指出错误所在,并给出完整程序。
(10分)
libraryieee;
useieee.std_logic_1164.all;
ENTITYMAXis
port(al,a2,a3,s0,sl:
inbit;
outy:
outbit);
endmax;(20
architectureoneofmaxis
componentmux21a
port(a,b,s:
instd_logic;
y:
outstd_logic);
endcomponent;(2')
signaltempstd_logic;(2‘)
begin
ul:
mux21aportmap(a2,a3,s0,temp);(2')
u2:
mux21aportmap(al,temp,sl,outy);(2‘)
endone;
1.己知电路原理图如下,请用VHDL语言编写其程序
答:
libraryieee;
useieee.std_logic_l164.all;
entitymux21is
port(a,b,s:
inbit;
y:
outbit);
endmux21;(4')
architectureoneofmux21is
singled,e:
bit;
begin
d<=aand(not)s;
e<=bands;
y<=dore;
endone;
2.设计一个带有异步清零功能的十进制计数器。
计数器时钟elk上升沿有效、清零端CLRN、进位输出
COo
COUNTER10
CLKDOUT[3..O]
CLRNCO
1
答:
libraryieee;
useieee.std_logic_l164.all;
entitycounter10is
port(clk,CLRN:
instd_logic;
(50
(3‘)
dout:
outintegerrange0to9);
endcounter10;
architecturebehavofcounter10IS
begin
process(clk)
variableent:
integerrange0to9;begin
IFCLRN=OTHEN
CNT:
=0;
ELSIF
clk^'l'andclk'eventthen
ifcnt=9then
cnt:
=O;
else
cnt:
=cnt+l;
endif;
endif;
dout<=cnt;
endprocess;
endbehav;
(70
3.1)用VHDL语言编写半加器和或门器件的程序,如图所示:
H_ADDE:
R
RCO
BSO
OR2A
RC
一
—
B
答:
半加器程序:
libraryieee;
useieee.std_logic_l164.all;
entityh_adderis
port(a,b:
instd_logic;
co,so:
outstd_logic);
endh_adder;
architectureoneofh_adderis
begin
so<=not(axor(notb));
co<=aandb;
endone;
或门程序:
libraryieee;
useieee.std_logic_1164.all;
entityor2ais
port(a,b:
instd_logic;
c:
outstd_logic);
endor2a;
architectureoneofor2ais
begin
c<=aorb;
endone;
2)在上道题目的基础上用元件例化语句设计1位全加器。
(2')
(30
主程序:
libraryieee;
useieee.std_logic_l164.all;
entityf_adderis
port(ain,bin,cin:
instd_logic;cout,sum:
outstd_logic);
endentityCadder;
architecturefdlofOdderis
componenth_adder
port(a,b:
instd_logic;
co,so:
outstd_logic);
endcomponent;(5')
componentor2a
port(a,b:
instd_logic;
c:
outstd_logic);
endcomponent;
signald,e,f:
std_logic;
begin
ul:
h_adderportmap(a=>ain,b=>bin,co=>d,so=>e);
u2:
h_adderportmap(a=>e,b=>cin,co=>f,so=>sum);
u3:
or2aportmap(d,f,cout);
endfdl;(50
1.试用VHDL语言编程实现一个总线开关,其真值表如下:
输入
输出
en
select
A0-A6
B0-B6
Y0-Y6
,0'
,x'
这zzzzzzz”
T
,0'
A
T
T
B
1.总线开关的参考程序如下:
LIBRARYieee;
USEieee.std_logic_l164.all;(1')
ENTITYaaaIS
PORT(en,select:
INSTD_LOGIC;
A,B:
INSTD_LOGIC_VECTOR(6DOWNTO0);
Y:
OUTSTD_LOGIC_VECTOR(6DOWNTO0)
ENDaaa;(4')
ARCHITECTUREarOFaaaIS
BEGIN
PROCESS(en,select)
BEGIN
IFen=,0,THENYVZZZZZZZ”;
ELSIFen=TTHEN
IFselect二'O'THENY<=A;
ELSIFselect二TTHENY<=B;
ENDIF;
ENDIF;
ENDPROCESS;
ENDar;(5‘)
2.试用VHDL语言编程实现「个MIO计数器,要求该计数器有一个时钟输入端elk,一个复位端rst(低电平复位),…个使能端en(高电平时允许计数),…个“计数到”输出端cout,…个4位二进制当前计数值输出口q;cout端仅当计数满的…个时钟周期输出高电平,其余时刻全保持低电平。
2.M10计数器参考程序:
LIBRARYieee;
USEieee.std_logic_1164.all;
USEieee.std_logic_arith.all;
USEieee.std_logic_unsigned.all;(1')
ENTITYaaaIS
PORT(clk,rst,en:
INSTD_LOGIC;
cout:
OUTSTD_LOGIC;
q:
BUFFERSTD_LOGIC_VECTOR(3DOWNTO0)
);
ENDaaa;(4')
ARCHITECTUREbdOFaaaIS
BEGIN
PROCESS(clk,reset,en)
BEGIN
IF(rst=,O,)THENq<="0000n;
ELSIF(clk'eventANDelk二T)THEN
IFen^TTHEN
IF(q=9)THENq<=n0000n;
ELSEq<=q+l;
ENDIF;
ENDIF;
ENDIF;
ENDPROCESS;
3.请用VHDL语言编程,用一个状态机模型实现一个七段码LED字符发生器。
该电路有一个复位输入端RST,—个时钟输入端CP,—组七段码输出端a~g。
在LED上七个段的排列位置如图所示。
该电路的功能为,当复位输入端RST为低电平时,输出端口输出全零,无显示;当RST为高电平时,在时钟信号CP的每个上升沿,输出端依次轮流输出5个字符“HAPPY”的七段码(共阴极接法),周而复始。
3.用VHDL语言编程实现一个LED字符发生器参考程序:
LIBRARYieee;
USEieee.std_logic_l164.ALL;
ENTITYgeneIS(1‘)
PORT(rst,cp:
INSTD_LOGIC;
a,b,c,d,e,f,g:
OUTSTD_LOGIC
);(1‘)
ENDgene;
ARCHITECTUREaaOFgeneIS
TYPEstateIS(sO,sl,s2,s3,s4,s5);
SIGNALpstate:
state;
SIGNALdout:
STD_LOGIC_VECTOR(6DOWNTO0);(2’)
BEGIN
prl:
PROCESS(cp,rst,)
BEGIN
IFrst='O*THENpstate<=s0;
ELSIF(cp*eventANDcp=!
0')THEN
CASEpstateIS
WHENs0=>pstate<=sl;
WHENsl=>pstate<=s2;
WHENs2=>pstate<=s3;
WHENs3=>pstate<=s4;
WHENs4=>pstate<=s5;
WHENs5=>pstate<=sl;
WHENOTHERS=>pstate<=s0;
ENDCASE;
ENDIF;
ENDPROCESS;(50
pr2:
PROCESS(pstate)
BEGIN
CASEstateIS
WHENsO=>dout<=n0000000n;—无显示
WHENsi=>dout<=H0110111";一“H"
WHENs2=>dout<=,'11101ir,;一“A”
WHENs3=>doutv=”1100111”;—“P"
WHENs4=>doutv=”1100111”;—“P"
WHENs5=>dout<="0111011";一“Y"
WHENOTHERS=>dout<=n0000000n;-无显示
ENDCASE;
ENDPROCESS;(50
a<=dout(6);b<=dout(5);c<=dout(4);d<=dout(3);e<=dout
(2);f<=dout(l);g<=dout(0);
ENDaa;(10
2•试用VHDL语言和进程语句,编程实现…个3-8译码器。
该译码器的功能为,当使能信号EN为低电平时,输出端Y7〜Y0全为高电平(没有输出端被选中);
当EN为高电平时,每…种ABC的输入状态组合能惟一地选中一路输出(被选中的端输出低电平)。
真值表如下:
输
入
输
出
A
B
c
EN
Y7
Y6
Y5
Y4
Y3
Y2
Y1
Y0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
1
1
1
1
1
1
1
1
0
1
0
1
0
1
1
1
1
1
1
0
1
1
0
1
1
1
1
1
1
1
0
1
1
1
1
0
0
1
1
1
1
0
1
1
1
1
1
0
1
1
1
1
0
1
1
1
1
1
1
1
0
1
1
0
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
X
X
X
0
1
1
1
1
1
1
1
1
LIBRARYieee;
USE
ieee.std_logic_1164.ALL;
T
ENTITY
ym38
IS
V
PORT(
a,
b,c,en:
IN
std_logic;
y
y
OUT
std_logic_vector(7DOWNTO0);
y
END
丿,
ym38;
ARCHITECTURE
arc38
OF
ls273IS
V
BEGIN
PROCESS(en)V
SIGNALdin:
std_logic_vector(7DOWNTO0);1'
BEGIN
din<=a&b&c&en;V
WITHdinSELECT
yv二''11111110"WHEN“0001";
”11111101”
WHEN
“0011”;
”11111011"
WHEN
“0101”;
”11110111"
WHEN
“0111";
”11101111"
WHEN
T001”;
”11011111"
WHEN
T011”;
”10111111”
WHEN
T101";
”01111111”
WHEN
“1111”;
"llllllll"
WHEN
OTHERS;
ENDPROCESS;
ENDarc38