翻译基于DSP的单芯片多处理器的通信应用的解决方案.docx

翻译基于DSP的单芯片多处理器的通信应用的解决方案.docx

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翻译基于DSP的单芯片多处理器的通信应用的解决方案

ASINGLE-CHIPMULTIPROCESSORDSPSOLUTIONFOR

COMMUNICATIONAPPLICATIONS

DavidRegenold

IntelCorporation

6505W.ChandlerBlvd.,M/SCH11-91

Chandler,Arizona85226

ABSTRACT

ThispaperpresentsanoverviewofanarchitectureforasinglechipmultiprocessorDSPsolutionforcommunicationsapplications.Theintegratedcircuitwasdesignedtohandletheprotocolanddata-pumpfunctionsnecessarytoimplementhigh-speedmodemandaudiotasks.Thechipconsistsofa186microcontrollerwithtwoDigitalSignalProcessing（DSPs）coprocessors.Itinterfaceswithastandard186busandhasaportforcommunicatingwithacustomCODEC,the80127.

INTRODUCTION

Computerconnectivityisaneverexpandingandpervasivemarket.StandardPOTS-lineMODEMScontinuetobepushedtohigherfrequenciesevenastheneedforhandlingsimultaneousvoiceemerges.Atthesametime,wirelesscapabilitiesareemergingandtheconceptofwirelessemailisbecomingarealitywiththeadventofpacketradionetworkssuchasMobitex,ArdisandCellularDigitalPacketData（CDPD）.

Toaddressthesemarkets,theCommunicationsProductsDivisionofIntelhasdevelopedachip-setspecificallyarchitectedtomeetthegrowingMIPSdemandsoftheemergingcommunicationsapplications.Thechipsetconsistsofthe80127CODEC,whichwaspresentedatlastyear'sASICconference,andthe8OC186CPcontroller/DSPwhichwillbepresentedhere.

DetailedArchitecture

The80C186CPisahighlyintegratedmicrocontrollerderivedfromthe80C186EBandprimarilytargetedtowardshighenddatacommunicationapplicationslikehighspeedmodems（v.34rates）andaudioprocess-ing.Toafirstorderitissoftwarecompatiblewiththe80C186EB.However,the8OC186CPenhancestheEBwiththeadditionofahighperformanceDigital-Signal-Processingcoprocessorandaversatileandflexibleperipheralsetdesignedtoeffectivelyinterfacewiththenecessarycommunicationchannels,suchasana-logCODECs,andISAorPCMCIAbuses.

Figure1showstheblockdiagramofthe8OC186CParchitecture.Asthediagramindicates,the80C186CP

isbuiltaroundtwointernalbusesknownastheF-busandtheE-bus.TheF-busisthestandardinternalbusfoundonall80C186Exproliferationsandisusedfordatatransfersbetweenthe80C186core,theexternalAddress/Databusandthe80C186peripherals.Itisa20-bitbuswhich,liketheexternalbus,multiplexesthe16-bitdatawith20-bitsofaddress.

ThemajorityoftheperipheralsattachedtotheF-busareidenticaltothosefoundonthe80C186EB.TheyincludetheEB'schip-selectunit,timerunit,interruptunit,parallelportunit,andserial-portunit（theEBhadtwo）.Theclockpower-managementunitissimilartothatfoundonthe80Cl86EB,butithasbeensubstantiallymodifiedaswillbediscussedlater.TheEXcoreandallmodulesontheF-busareclockedat20.736MHzinthetargetapplications.

NewF-busperipheralsnotfoundonthestandard80C186EBincludeahost-interfaceunitandanHDLCaccelerator.Thehost-interfaceunitallowsthe80C186CPtobeattachedtoeitheranISAoraPCM-CIAbus.Itcontainsa16550emulator,whichmakesthe8OC186CPappeartothehostasmerelya16550UART.Inactuality,thedatatransferredbetweenthe16550emulatorisnotserializedasinarealUART,buteithertakenfromthecoresinthe8OC186CPorpresentedtothemfordatamanipulationasrequiredbythecommunicationstandardbeingimplemented.WheninPCMCIAmode,theunitsupportsaccessestotheCardInformationServices（CIS）memoryandcontainstheotherspecialfunctionregistersdefinedbythePCMCIAstandard.

DatabeingtransferredacrossthehostinterfacemustsometimesbeHDLCencodedordecodeddependingagainonthestandardbeingimplemented.Forthispurpose,anHDLCacceleratorisprovidedtoalleviatetheEXcorefromtheintensebitmanipulationthatwouldotherwiseberequired.UnlikeatypicalHDLCcontrollerthatreceivesandtransmitsdataserially,thisunitreceivesdatafromtheF-businparallelformsincetheEXcoreisdealingexclusivelywithparalleldata.TheHDLCacceleratorviewsthedataasaserialbitstreamandperformsthetasksofCRCgeneration,zerobitinsertionordeletion,anderrordetection.

AnothermoduleontheF-busnotfoundinother80C186EXproductsisthecoprocessor-interfaceblock（orarbiter）.ThisunitisdiscussedaftertheDSPcoprocessor.Sufficeittosayfornowthatthismoduleplaysapivotalroleinthe8OC186CPchipandactsasthecentralpointofcommunicationbetweenthe80C186sideofthecontrollerandtheDSPcoprocessor.TheDSPcoprocessorconsistsprimarilyoftwoDSPcoresknownastheEP+cores,severalmemorybanksforprogramanddatastorage,andsomeperipherals,suchasaCODECinterfaceandaViterbiaccelerator.

AblockdiagramofanEP+isshowninFigure2.TheseDSPcoresaresimpleMultiplyandAccumulate（MAC）enginescapableofexecutingapeakrateofoneMACperclockcycle.Forthetargetapplication,the80C186CPisclockedat20.736MHz,whichresultsinapeakthroughputofmorethan40millionMACSpersecond.

TheEP+ALUisfedfromtwointernal256-wordRAMsthatcontaindataandcoefficientsrequiredbythealgorithms.One16-bitwordcanbefetchedfromeachSRAMeveryclockcycleinordertofeedtheMACengine.Themultiplierproducesa32-bitproductthatisaccumulatedina32-bitregister.Additionalhardwareisavailabletoassistdivision.

Accesstomemorybeyondtheinternal512wordsisachievedthroughamemory-expansionunitthatsitsonan8-wordparallelportoftheEP+calledtheEXTbus.Throughthisexpansionport,theEP+canaccessupto64kwordsofadditionaldata（althoughonly3.5kisactuallypresentinthisimplementation）.TheadditionaldatamaybepresentonaprivatebusoftheparticularEP+ormayresideonthesharedE-bus.DatacanbeaccessedthroughthisportatapeakrateofonewordperclockcycleandreplacesoneoftheDSP’sinternalSRAMswheninuse.

TheDSPsaresuppliedtheirprogramcodeanddatathroughseveralbanksofSRAM.SincetheyareofaHarvardarchitecture,theyeachhavetheirownseparateprogrambusadseparateprivatedatabus.Four512-wordSRAMsareprovidedforprogrampurposesandfour256-wordSRAMsareprovidedfordatapurposes.AnyofthefourprogramRAMscanbeconnectedtotheprogrambusofeitherEP+whileanyofthefourdataRAMscanbeconnectedtotheprivatedatabusofeitherEP+.

TheE-busisasingle-clock-cycle-transferbusconsistingof16addressbitsand16databits.ItmaybeaccessedbyeitherEP+coreortheEXcore.TheDSPscantransferdataacrossthebusatarateofonewordperclockcycle.However,theEXcoreisstilllimitedtoonewordeveryfourclockcyclesduetothelimitationsoftheF-bus.AnyoftheprogramanddatamemorybankscanbeconnectedtotheE-bussothatanyofthethreecorescanarbitrateforaccesstothem.

ProgrammingofthememoryconfigurationoccursthroughtheIPCBblock.Thismodulealsoactsasacentral-switchingofficeforinterrupts.Interruptsignalsfromalldifferentpartsofthesystemconvergeonthisunitandaresenttoanyoneofthethreeprocessorsaccordingtoprogrammingofaregisterwithintheunit.

AttachedtooneoftheDSPsisaViterbiAccelerator.TheViterbialgorithmisencounteredfrequentlyincommunicationsbuthaslittletodowithMultiply/AccumulatesandthusisnotimplementedefficientlybytheEP+architecture.TheEP+usesthismodulebysimplywritingaseriesofdatapairstoitandthenreadingtheresultingmaximumorminimumofthesumsofthedatapairsandthecorrespondingindex.

Datareceivedacrossacommunicationsmedia（eitherwiredorwireless）comesintothe8OC186CPfromanAnalogFrontEnd（the80127AFE）viatheHigh-Speed-Synchronous-SerialPort（HSSSP）.ThisunitusesaninterfacefoundonmanyindustrystandardDSPstocommunicatewiththeAFE.TheHSSSPhasaccesstotwomore256-wordSRAMsbetweenwhichitfetchesandstoresdata.ThisallowstheHSSSPtotransmitandreceivetwoblocksof256wordsinfull-duplexmodewithoutinterventionfromanyoftheprocessorsonchip.ThemoreusualcaseistohavetheHSSSPtransmitandreceivetwoblocksof128wordsinfullduplexmodefromasingleSRAMwhiletheEP+workswiththedatapreviouslyreceivedorsoontobetransmittedintheotherSRAM.

Thelastmajorblockonthe80C186CPisthecoprocessorinterfacemodule.Thisblockismultifunctional.ItallowstheEXcoretoaccessallofthememoryandSpecialFunctionRegistersresidingontheE-busasaregionintheC186's1MByteaddressrange.Italsoactsasthearbitrationunitbetweenthethreeon-chipprocessorsforaccesstotheE-busanditcontainsastatusregisterthroughwhichtheEXcorecanmonitoractivityontheE-bus.Butitsmostimportantfunctionisthatofafly-byDMAunittotransferdatafromtheF-bustotheE-busorvisa-versa.

ThecodeanddatamemoryrequirementsoftheDSPalgorithmsrunningonthetwoEPsareusuallylargerthanthefeasibleonchipmemory.Therefore,afastandlowoverheadmethodofdownloadinghploadingcodeanddatatotheonchipmemoriesfromoff-chipprogrammemoryisessential.Thisisaccomplishedviathefly-byDMAwhichresidesinthecoprocessor-interfaceunit.AnyofthethreeE-busmasterscanutilizetheDMAbyprogrammingthenecessaryparameters,suchasthestartingaddress,endingaddress,andwordcount.

Theprogrammingofthefly-byDMAtakesadvantageofthefactthattheDSPfirmwarerunningontheDSPsisfairlypredictable.Thatis,thecurrenttasksrunningontheDSPsshouldknowwhichsoftwaremodulesaremostlikelytobeneedednext.Thecur-renttask,throughawritetoaregister,informstheDMAunitthatitwill