基于粒子群算法的PID控制器的FPGA实现源程序精品文档完整版.docx
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基于粒子群算法的PID控制器的FPGA实现源程序精品文档完整版
附录A基于粒子群算法的PID控制器的FPGA实现源程序
--pso算法控制模块源程序
libraryieee;
useieee.std_logic_1164.all;
--useieee.std_logic_arith.all;
useieee.std_logic_unsigned.all;
--uselgQQ_pso.all;
entitycontrolis
port（ctr_clk_P,ctr_ctr_res_l:
instd_logic;
ov1_1:
instd_logic;--初始化结束信号
ov2_1:
instd_logic;--从初始化后的32个个体中选择全局最优结束信号
ov3_1:
instd_logic;--局部，全局最优更新结束信号
ov4_1:
instd_logic;--个体速度计算并判断阀值结束信号
ov5_1:
instd_logic;--个位置计算并判断阀值结束信号
st2_1:
outstd_logic;--启动从初始化后的32个个体中选择全局最优选择模块
st3_1:
outstd_logic;--启动局部，全局最优更新模块
st4_1:
outstd_logic;--启动个体速度计算并判断阀值模块
st5_1:
outstd_logic;--启动个位置计算并判断阀值模块
cmux1:
outstd_logic;
cmux2:
outstd_logic;
cmux3:
outstd_logic;
cmux4:
outstd_logic;
cmux5:
outstd_logic;
random_clk:
outstd_logic;
wr_1,rd_1:
outstd_logic;
lz_cnt:
outstd_logic_vector（4downto0）;
iterance:
outstd_logic_vector（7downto0）
）;
endcontrol;
architecturebehavioralofcontrolis
typestatesis（idle,st1,st2,st3,st4,st5,st6,stop）;
signalcurrent_state:
states;
signalflag:
std_logic;--mux5
signallzcnt:
std_logic_vector（4downto0）;
signaliter:
std_logic_vector（7downto0）;
begin
process（ctr_clk_P,ctr_res_1,current_state）--系统主状态机
begin
ifctr_res_1='1'then
current_state<=idle;
elsifctr_clk_P'eventandctr_clk_P='1'then
casecurrent_statesis
whenidle=>--系统复位
wr_1<='1';rd_1<='0';
st2_1<='0';st3_1<='0';
cmux1<='0';cmux2<='0';
cmux3<='0';cmux4<='0';--mux5<='0';
random_clk<='0';flag<='0';
iter<=（others=>'0'）;
lzcnt<=（others=>'0'）;
current_states<=st1;
whenst1=>--群体初始化
wr_1<='1';rd_1<='0';
st2_1<='0';st3_1<='0';
st4_1<='0';st5_1<='0';
cmux1<='0';cmux2<='0';
cmux3<='0';cmux4<='0';random_clk<='0';--mux5<='0';
ifov1_1='1'then
current_state<=st2;
wr_1<='0';rd_1<='1';
elsecurrent_state<=st1;
endif;
whenst2=>--从初始化后的32个个体中选择全局最优
wr_1<='0';rd_1<='1';
st2_1<='1';st3_1<='0';
st4_1<='0';st5_1<='0';
cmux1<='1';cmux2<='0';
cmux3<='1';cmux4<='0';random_clk<='0';--mux5<='0';
ifov2_1='1'then
current_state<=st3;
sta_sel_1<='0';
elsecurrent_state<=st2;
endif;
whenst3=>--局部，全局最优更新
wr_1<='0';rd_1<='1';
st2_1<='0';st3_1<='1';
st4_1<='0';st5_1<='0';
cmux1<='1';cmux2<='1';
cmux3<='1';cmux4<='1';random_clk<='1';
ifov3_1='1'then
current_state<=st4;st3_1<='0';
elsecurrent_state<=st3;
endif;
whenst4=>--个体速度计算并判断阀值
wr_1<='0';rd_1<='0';
st2_1<='0';st3_1<='0';
st4_1<='1';st5_1<='0';
cmux1<='1';cmux2<='1';
cmux3<='1';cmux4<='1';random_clk<='1';
ifov4_1='1'then
current_state<=st5;st4_1<='0';
elsecurrent_state<=st4;
endif;
whenst5=>--个体位置计算并判断阀值
wr_1<='0';rd_1<='0';
st2_1<='0';st3_1<='0';
st4_1<='0';st5_1<='1';
cmux1<='1';cmux2<='1';
cmux3<='1';cmux4<='1';
random_clk<='1';
ifov5_1='1'then
st5_1<='0';
flag<=notflag;
ifflag='1'then
current_state<=st6;wr_1<='1';
elsecuttent_state<=st4;
endif;
elsecurrent_state<=st5;
endif;
whenst6=>--新个体位置，速度，局部最优更新后的数据存储
wr_1<='0';rd_1<='0';
st2_1<='0';st3_1<='0';
st4_1<='0';st5_1<='0';
cmux1<='1';cmux2<='1';
cmux3<='1';cmux4<='1';
random_clk<='0';
iflzcnt="11111"then
lzcnt<="00000";
iter<=iter+1;
else
lzcnt<=lzcnt+1;
endif;
ifiter="01111111"then
current_state<=stop;
elsecuttent<=st3;
endif;
whenstop=>--迭代结束
cuttent_state<=stop;
wr_1<='0';rd_1<='0';
st2_1<='0';st3_1<='0';
st4_1<='0';st5_1<='0';
cmux1<='0';cmux2<='0';
cmux3<='0';cmux4<='0';
whenothers=>
current_state<=stop;
endcase;
endif;
endprocess;
cmux5<=flag;
iterance<=iter;
lz_cnt<=lzcnt;
endBehavioral;
--初始化粒子个体模块
libraryieee;
useieee.std_logic_1164.all;
--useieee.std_logic_arith.all;
useieee.std_logic_unsigned.all;
usework.lgQQ_pso.all;
entityini_particleis
port（ckl_P,res_1:
instd_logic;
ad_msb:
instd_logic;
address:
outstd_logic_vector（m-1downto0）;--（m-1downto0）;
p:
outstd_logic_vector（31downto0）;
v:
outstd_logic_vector（23downto0）;
over_1:
outstd_logic
）;
endini_particle;
architecturebehavioralofini_particleis
signalz:
std_logic_vector（31downto0）;
signalqz:
std_logic;
signalcnt:
std_logic_vector（m-1downto0）;
begin
process（clk_P,res_1）
begin
ifres_1='1'then
z<="01010010010001010010101000011101";
cnt<=（others=>'0'）;--"0000";
over_1<='0';
elsifclk_P'eventandclk_P='1'then
z（31downto1）<=z（30downto0）;
z（0）<=qz;
p<=z
（1）&z（3）&z（4）&z（5）&z（7）&z（8）&z（10）&z（12）&z（13）&
z（15）&z（17）&z（21）&z（23）&z（27）&z（30）&z（31）&z（0）&z
（2）&z（6）
&z（9）&z（11）&z（14）&z（16）&z（18）&z（19）&
z（20）&z（22）&z（24）&z（26）&z（28）&z（29）;
v<=z
（1）&z（3）&z（5）&z（7）&z（9）&z（7）&z（11）&z（13）&z（15）&
z（17）&z（19）&z（21）&z（23）&z（0）&z
（2）&z（4）&z（6）&z（8）&
z（10）&z（12）&z（14）&z（16）&z（18）&z（20）&z（22）;
cnt<=cnt+1;
address<=cnt;--ad_msb&
ifcnt="11111"then
over_1<='1';
endif;
endif;
endprocess;
qz<=z（31）xorz（6）xorz
（1）xorz（4）xorz（0）;
endBehavioral;
--多路选择器Mux1模块源程序
libraryieee;
useieee.std_logic_1164.all;
--useieee.std_logic_arith.all;
--useieee.std_logic_unsigned.all;
--usework.canshu.all;
entitymux1is
port（mux_ctr1,mux_ctr2:
instd_logic;
xi1,xi2:
instd_logic_vector（31downto0）;
vi1,vi2:
instd_logic_vector（23downto0）;
ad1,ad2,ad3:
instd_logic_vector（4downto0）;
wad:
outstd_logic_vector（4downto0）;
rad:
outstd_logic_vector（4downto0）;
vi:
outstd_logic_vector（23downto0）;
xi:
outstd_logic_vector（31downto0）
）;
endmux1;
architectureBehavioralofmux1is
begin
process（mux_ctr1,mux_ctr2,xi1,xi2,vi1,vi2,ad1,ad2,ad3）
begin
ifmux_ctr1='0'then--接收初始化模块的数据
xi<=xi1;vi<=vi1;
wad<=ad1;
else--接收经过一代更新的新个体数据
xi<=xi2;vi<=vi2;
wad<=ad3;
endif;
ifmux_ctr2='0'then--读取刚初始化后的数据地址
rad<=ad2;
else--读取新个体数据地址
rad<=ad3;
endif;
endprocess;
endarchitecture;
--多路选择器Mux2模块源程序
libraryieee;
useieee.std_logic_1164.all;
--useieee.std_logic_arith.all;
--useieee.std_logic_unsigned.all;
--usework.canshu.all;
entitymux2is
port（mux_ctr:
instd_logic;
pbxi1,pbxi2:
instd_logic_vector（31downto0）;
fpbxi1,fpbxi2:
instd_logic_vector（23downto0）;
pbxi:
outstd_logic_vector（31downto0）;
fpbxi:
outstd_logic_vector（23downto0）
）;
endmux2;
architectureBehavioralofmux2is
begin
ifmux_ctr='0'then--接收初始化模块的数据
pbxi<=pbxi1;
fpbxi<=fpbxi;
else--接收经过一代更新的新个体数据
pbxi<=pbxi2;
fpbxi<=fobxi;
endif;
endprocess;
endarchitecture;
--多路选择器Mux3模块源程序
libraryieee;
useieee.std_logic_1164.all;
--useieee.std_logic_arith.all;
--useieee.std_logic_unsigned.all;
--usework.canshu.all;
entitymux3is
port（mux_ctr:
instd_logic;
xi:
instd_logic_vector（31downto0）;
fxi:
instd_logic_vector（23downto0）;
xi1,xi2:
outstd_logic_vector（31downto0）;
fxi1,fxi2:
outstd_logic_vector（23downto0）
）;
endmux3;
architectureBehavioralofmux3is
begin
process（mux_ctr,xi,fxi）
begin
ifmux_ctr='0'then--接收刚初始化的数据
xi1<=xi;xi2<=（others=>'0'）;
fxi1<=fxi;fxi2<=（others=>'0'）;
else--接收经过一代更新的新个体数据
xi2<=xi;xi1<=（others=>'0'）;
fix2<=fxi;fxi1<=（others=>'0'）;
endif;
endprocess;
endarchitecture;
--从初始粒子群中选择一个全局最优解模块源程序
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entitygbestis
port（clk_P,stat_1:
instd_logic;
res_1:
instd_logic;
x1x2:
instd_logic_vector（31downto0）;--（31downto0）;
x_fit:
instd_logic_vector（23downto0）;--（mdownto0）;
address:
outstd_logic_vector（4downto0）;
gbest:
outstd_logic_vector（31downto0）;--（31downto0）;
gb_fit:
outstd_logic_vector（23downto0）;
over_1:
outstd_logic
）;
endgbest;
architectureBehavioralofgbestis
signalgfit:
std_logic_vector（23downto0）;
signalcnt:
std_logic_vector（4downto0）;
typestatesis（idle,st1,stop）;
signalcurrent_state:
states;
begin
process（res_1,clk_p,current_state,start_1,x_fit,gfit）--cnt
begin
ifres_1='1'then
current_state<=idle;
gb_fit<=（others=>'1'）;
gfit<=（others=>'1'）;
gbest<=（others=>'1'）;
over_1<='0';
elsifclk_P'eventandclk_P='1'then
casecurrent_stateis
whenidle=>over_1<='0';
cnt<=（others=>'0'）;
ifstart_1='1'then
current_state<=st1;snt<=cnt+1;
elsecurrent_state<=idle;
endif;
whenst1=>over_1<='0';
ifgfit>x_fitthen
gbest<=x1x2;
gfit<=x_fit;
endif;
cnt<=cnt+1;
ifcnt="11111"then
current_state<=stop;
elsecurrent_state<=st1;
endif;
whenstop=>over_1<='1';
current_state<=stop;
whenothers=>over_1<='0';
current_state<=idle;
endcase;
endif;
gb_fit<=gfit;
endprocess;
address<=cnt;
endBehavioral;
--粒子局部最优更新模块源程序
libraryieee;
useieee.std_logic_1164.all;
entitypbestis
port（clk_P,start_1:
instd_logic;
res_1:
instd_logic;
lz_cnt:
instd_logic_vector（4downto0）;
xin,pbin:
instd_logic_vector（31downto0）;--（m-1downto0）;
fxi,fpbi:
instd_logic_vector（23downto0）;--（mdownto0）;
xio,pbio:
outstd_logic_vector（31downto0）;--（m-1downto0）;
fpbio:
outstd_logic_vector（23downto0）;--fxio,
fgb:
instd_logic_vector（23downto0）;
gb:
instd_logic_vector（31downto0）;
iter:
instd_logic_vector（7downto0）;
gbest:
outstd_logic_vector（31downto0）;--（m-1downto0）;
gbfit:
outstd_logic_vector（23downto0）;
over_1:
outstd_logic
）;
endpbest;
architectureBehavioralofpbestis
signalmaxfit:
std_logic_vector（23downto0）;
signalmax:
std_logic_vector（31downto0）;
typestatesis（idle,st1,st3）;
signalcurrent_state:
states;
begin
process（res_1,clk_p,current_state,start_1,max,maxfit,xin）
begin
ifres_1='1'then
current_state<=idle;
maxfit<=（others=>'1'）;
max<=（others=>'1'）;
elsifclk_P'eventandclk_P='1'then
casecurrent_stateis
whenidle=>over_1<='0';
ifstart_1='1'then
current_state<=st1;
ifiter="00000000"andlz_cnt="000000"then
max<=gb;
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