多功能数字时钟VHDL源代码.docx
《多功能数字时钟VHDL源代码.docx》由会员分享，可在线阅读，更多相关《多功能数字时钟VHDL源代码.docx（17页珍藏版）》请在冰豆网上搜索。
多功能数字时钟VHDL源代码
源代码：
Alert模块：
libraryieee;
useieee.std_logic_1164.all;
entityalertis
port（dip:
instd_logic_vector（3downto0）;
h1,h0,m1,m0,s1,s0:
instd_logic_vector（3downto0）;------输入秒、分高/低位信号
nao_h_h,nao_h_l,nao_m_h,nao_m_l:
instd_logic_vector（3downto0）;
clk:
instd_logic;
q500,qlk,q1khz:
outstd_logic）;
endalert;
architecturebehavofalertis
begin
process（clk）
begin
ifclk'eventandclk='1'then
ifm1="0101"andm0="1001"ands1="0101"then----当秒高位为5，低位为9时且分高位为5
ifs0="0001"ors0="0011"ors0="0101"ors0="0111"then---当分的低位为1或3或5或7时
q500<='1';----低频输出为1
else
q500<='0';----否则输出为0
endif;
endif;
ifm1="0101"andm0="1001"ands1="0101"ands0="1001"then---当秒高位为5，低位为9时且分高位为5，----分低位为9时，也就是“59分59秒”的时候“报时”
qlk<='1';-----高频输出为1
else
qlk<='0';
endif;
endif;
endprocess;
process（h1,h0,m1,m0,nao_h_h,nao_h_l,nao_m_h,nao_m_l）
begin
ifdip（0）='1'andh1=nao_h_handh0=nao_h_landm1=nao_m_handm0=nao_m_lthen
q1khz<='1';
else
q1khz<='0';
endif;
endprocess;
endbehav;
braz模块：
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
useieee.std_logic_arith.all;
entitybrazis
port（dip:
instd_logic_vector（3downto0）;
q500,qlk,q1khz:
instd_logic;
f1khz,f500hz:
instd_logic;
braz:
outstd_logic）;
endentity;
architecturebehaveofbrazis
begin
process（q500,qlk,dip）
begin
ifdip="0010"ordip="1110"ordip="1010"ordip="0110"thenbraz<='1';
endif;
ifq500='1'thenbraz<=f500hz;
elsifqlk='1'orq1khz='1'thenbraz<=f1khz;
elsebraz<='1';
endif;
endprocess;
endbehave;
秒计数模块：
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
useieee.std_logic_arith.all;
entitycount60is
port（carry:
instd_logic;
one:
outstd_logic_vector（3downto0）;
ten:
outstd_logic_vector（3downto0）;
full:
outstd_logic）;
endcount60;
architecturebehaveofcount60is
begin
process（carry）
variableones:
std_logic_vector（3downto0）:
="0000";
variabletens:
std_logic_vector（3downto0）:
="0000";
begin
ifrising_edge（carry）then
ones:
=ones+1;
if（tens="0101"andones="1010"）thenones:
=（others=>'0'）;tens:
=（others=>'0'）;full<='1';
elsif（ones="1010"）thentens:
=tens+1;ones:
="0000";full<='0';
endif;
endif;
one<=ones;
ten<=tens;
endprocess;
endbehave;
显示模块：
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
useieee.std_logic_arith.all;
entitydisplayis
port（clk:
instd_logic;
a,b,c,d:
instd_logic_vector（3downto0）;
mux_out:
outstd_logic_vector（3downto0）;
wei1,wei2,wei3,wei4:
outstd_logic）;
enddisplay;
architecturebehaveofdisplayis
signalsel:
integerrange0to3;
begin
process（a,b,c,d,clk）
begin
ifrising_edge（clk）then
sel<=sel+1;
caseselis
when0=>mux_out<=a;
wei4<='0';wei3<='1';wei2<='1';wei1<='1';
when1=>mux_out<=b;
wei4<='1';wei3<='0';wei2<='1';wei1<='1';
when2=>mux_out<=c;
wei4<='1';wei3<='1';wei2<='0';wei1<='1';
when3=>mux_out<=d;
wei4<='1';wei3<='1';wei2<='1';wei1<='0';
whenothers=>mux_out<="1100";
endcase;
endif;
endprocess;
endbehave;
消抖模块：
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entitydebounceis
port（key:
instd_logic_vector（3downto0）;
clk:
instd_logic;
key_valid:
outstd_logic）;
enddebounce;
architecturebehaveofdebounceis
begin
process（clk,key）
variablecnt:
integerrange0to31;
begin
if（key="0111"orkey="1011"orkey="1101"orkey="1110"）then
if（clk'eventandclk='1'）then
ifcnt=31then
key_valid<='1';--keypressed
else
key_valid<='0';--nokeypressed
cnt:
=cnt+1;--cntplusone
endif;
endif;
else
cnt:
=0;--nokeypressed,theconterreset
key_valid<='0';--nokeypressed
endif;
endprocess;
endbehave;
闹钟模块：
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
useieee.std_logic_arith.all;
entitynaozhongis
port（
key:
instd_logic_vector（3downto0）;
key_valid:
instd_logic;
nao_h_ten:
outstd_logic_vector（3downto0）;
nao_h_one:
outstd_logic_vector（3downto0）;
nao_m_ten:
outstd_logic_vector（3downto0）;
nao_m_one:
outstd_logic_vector（3downto0））;
endnaozhong;
architecturebehaveofnaozhongis
signalnao_h:
integerrange0to23:
=12;
signalnao_m:
integerrange0to59;
begin
process（key,key_valid）
begin
ifrising_edge（key_valid）then
if（key="1110"）then
if（nao_h>=23）thennao_h<=0;
elsenao_h<=nao_h+1;
endif;
endif;
endif;
endprocess;
process（key,key_valid）
begin
ifrising_edge（key_valid）then
if（key="0111"）then
if（nao_m>=59）thennao_m<=0;
elsenao_m<=nao_m+1;
endif;
endif;
endif;
endprocess;
process（nao_h）
begin
casenao_his
when0|10|20=>nao_h_one<="0000";
when1|11|21=>nao_h_one<="0001";
when2|12|22=>nao_h_one<="0010";
when3|13|23=>nao_h_one<="0011";
when4|14=>nao_h_one<="0100";
when5|15=>nao_h_one<="0101";
when6|16=>nao_h_one<="0110";
when7|17=>nao_h_one<="0111";
when8|18=>nao_h_one<="1000";
when9|19=>nao_h_one<="1001";
whenothers=>nao_h_one<="1110";
endcase;
casenao_his
when0|1|2|3|4|5|6|7|8|9=>nao_h_ten<="0000";
when10|11|12|13|14|15|16|17|18|19=>nao_h_ten<="0001";
when20|21|22|23=>nao_h_ten<="0010";
whenothers=>nao_h_ten<="1110";
endcase;
endprocess;
process（nao_m）
begin
casenao_mis
when0|10|20|30|40|50=>nao_m_one<="0000";
when1|11|21|31|41|51=>nao_m_one<="0001";
when2|12|22|32|42|52=>nao_m_one<="0010";
when3|13|23|33|43|53=>nao_m_one<="0011";
when4|14|24|34|44|54=>nao_m_one<="0100";
when5|15|25|35|45|55=>nao_m_one<="0101";
when6|16|26|36|46|56=>nao_m_one<="0110";
when7|17|27|37|47|57=>nao_m_one<="0111";
when8|18|28|38|48|58=>nao_m_one<="1000";
when9|19|29|39|49|59=>nao_m_one<="1001";
whenothers=>nao_m_one<="1110";
endcase;
casenao_mis
when0|1|2|3|4|5|6|7|8|9=>nao_m_ten<="0000";
when10|11|12|13|14|15|16|17|18|19=>nao_m_ten<="0001";
when20|21|22|23|24|25|26|27|28|29=>nao_m_ten<="0010";
when30|31|32|33|34|35|36|37|38|39=>nao_m_ten<="0011";
when40|41|42|43|44|45|46|47|48|49=>nao_m_ten<="0100";
when50|51|52|53|54|55|56|57|58|59=>nao_m_ten<="0101";
whenothers=>nao_m_ten<="1110";
endcase;
endprocess;
endbehave;
译码输出模块：
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
useieee.std_logic_arith.all;
entityyimais
port（clk:
instd_logic;
bcd:
instd_logic_vector（3downto0）;
eight:
outstd_logic_vector（7downto0））;
endyima;
architecturebehaveofyimais
begin
process（clk）
begin
casebcdis
when"0000"=>eight<="11000000";
when"0001"=>eight<="11111001";
when"0010"=>eight<="10100100";
when"0011"=>eight<="10110000";
when"0100"=>eight<="10011001";
when"0101"=>eight<="10010010";
when"0110"=>eight<="10000010";
when"0111"=>eight<="11111000";
when"1000"=>eight<="10000000";
when"1001"=>eight<="10010000";
whenothers=>eight<="11111111";
endcase;
endprocess;
endbehave;
分频模块：
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned;
entityfenpinis
port（clk:
instd_logic;
f1khz:
outstd_logic）;
endfenpin;
architecturebehavoffenpinis
signalmid:
std_logic;
begin
process（clk）
variablecnum:
integerrange0to25000;
begin
if（clk'eventandclk='1'）then
cnum:
=cnum+1;
ifcnum=25000then
mid<=notmid;
cnum:
=0;
endif;
f1khz<=mid;
endif;
endprocess;
endbehav;
1000分频模块：
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
useieee.std_logic_arith.all;
entitydiv1000is
port（clk:
instd_logic;
f1hz:
outstd_logic）;
endentity;
architecturebehavofdiv1000is
signalcount:
integerrange0to1000;
begin
process（clk）
begin
ifrising_edge（clk）then
count<=count+1;
ifcount=1000thenf1hz<='1';
elsef1hz<='0';
endif;
endif;
endprocess;
endbehav;
分计数模块：
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
useieee.std_logic_arith.all;
entitymincountis
port（carry:
instd_logic;
key_valid:
instd_logic;
key:
instd_logic_vector（3downto0）;
ten:
outstd_logic_vector（3downto0）;
one:
outstd_logic_vector（3downto0）;
full:
outstd_logic）;
endmincount;
architecturebehaveofmincountis
signalmin:
integerrange0to59;
signalmin_temp:
integerrange0to59;
signalmin_temp1:
integerrange0to59;
begin
process（carry）
begin
ifrising_edge（carry）then
min_temp<=min_temp+1;
if（min_temp=59）then
full<='1';min_temp<=0;
else
full<='0';
endif;
endif;
endprocess;
process（key,key_valid）
begin
ifrising_edge（key_valid）then
if（key="1101"）then
min_temp1<=min_temp1+1;
if（min_temp1>=59）thenmin_temp1<=0;
endif;
endif;
endif;
endprocess;
process（min）
begin
min<=（min_temp+min_temp1）mod（60）;
caseminis
when0|10|20|30|40|50=>one<="0000";
when1|11|21|31|41|51=>one<="0001";
when2|12|22|32|42|52=>one<="0010";
when3|13|23|33|43|53=>one<="0011";
when4|14|24|34|44|54=>one<="0100";
when5|15|25|35|45|55=>one<="0101";
when6|16|26|36|46|56=>one<="0110";
when7|17|27|37|47|57=>one<="0111";
when8|18|28|38|48|58=>one<="1000";
when9|19|29|39|49|59=>one<="1001";
whenothers=>one<="1110";
endcase;
caseminis
when0|1|2|3|4|5|6|7|8|9=>ten<="0000";
when10|11|12|13|14|15|16|17|18|19=>ten<="0001";
when20|21|22|23|24|25|26|27|28|29=>ten<="0010";
when30|31|32|33|34|35|36|37|38|39=>ten<="0011";
when40|41|42|43|44|45|46|47|48|49=>ten<="0100";
when50|51|52|53|54|55|56|57|58|59=>ten<="0101";
whenothers=>ten<="1110";
endcase;
endprocess;
endbehave;
小时计数模块：
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
useieee.std_logic_arith.all;
entit
升级会员 