单片机外文翻译AT89C微控制器的指令.docx

单片机外文翻译AT89C微控制器的指令.docx

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单片机外文翻译AT89C微控制器的指令

AT89C2051MicrocontrollerInstructions

1.1Features

∙CompatiblewithMCS-51Products

∙2KbytesofReprogrammableFlashMemory

Endurance:

1,000Write/EraseCycles

∙2.7Vto6VOperatingRange

∙FullyStaticOperation:

0Hzto24MHz

∙Two-LevelProgramMemoryLock

∙128x8-BitInternalRAM

∙15ProgrammableI/OLines

∙Two16-BitTimer/Counters

∙SixInterruptSources

∙ProgrammableSerialUARTChannel

∙DirectLEDDriveOutputs

∙On-ChipAnalogComparator

∙LowPowerIdleandPowerDownModes

1.2Description

TheAT89C2051isalow-voltage,high-performanceCMOS8-bitmicrocomputerwith2KbytesofFlashprogrammableanderasablereadonlymemory（PEROM）.ThedeviceismanufacturedusingAtmel’shighdensitynonvolatilememorytechnologyandiscompatiblewiththeindustrystandardMCS-51instructionsetandpinout.Bycombiningaversatile8-bitCPUwithFlashonamonolithicchip,theAtmelAT89C2051isapowerfulmicrocomputerwhichprovidesahighlyflexibleandcosteffectivesolutiontomanyembeddedcontrolapplications.

TheAT89C2051providesthefollowingstandardfeatures:

2KbytesofFlash,128bytesofRAM,15I/Olines,two16-bittimer/counters,afivevectortwo-levelinterruptarchitecture,afullduplexserialport,aprecisionanalogcomparator,on-chiposcillatorandclockcircuitry.Inaddition,theAT89C2051isdesignedwithstaticlogicforoperationdowntozerofrequencyandsupportstwosoftwareselectablepowersavingmodes.TheIdleModestopstheCPUwhileallowingtheRAM,timer/counters,serialportandinterruptsystemtocontinuefunctioning.ThePowerDownModesavestheRAMcontentsbutfreezestheoscillatordisablingallotherchipfunctionsuntilthenexthardwarereset.

1.3PinConfiguration

1.4PinDescription

VCCSupplyvoltage.

GNDGround.

Port1

Port1isan8-bitbidirectionalI/Oport.PortpinsP1.2toP1.7provideinternalpullups.P1.0andP1.1requireexternalpullups.P1.0andP1.1alsoserveasthepositiveinput（AIN0）andthenegativeinput（AIN1）,respectively,oftheon-chipprecisionanalogcomparator.ThePort1outputbufferscansink20mAandcandriveLEDdisplaysdirectly.When1sarewrittentoPort1pins,theycanbeusedasinputs.WhenpinsP1.2toP1.7areusedasinputsandareexternallypulledlow,theywillsourcecurrent（IIL）becauseoftheinternalpullups.

Port1alsoreceivescodedataduringFlashprogrammingandprogramverification.

Port3

Port3pinsP3.0toP3.5,P3.7aresevenbidirectionalI/Opinswithinternalpullups.P3.6ishard-wiredasaninputtotheoutputoftheon-chipcomparatorandisnotaccessibleasageneralpurposeI/Opin.ThePort3outputbufferscansink20mA.When1sarewrittentoPort3pinstheyarepulledhighbytheinternalpullupsandcanbeusedasinputs.Asinputs,Port3pinsthatareexternallybeingpulledlowwillsourcecurrent（IIL）becauseofthepullups.

PortPin

AlternateFunctions

P3.0

RXD（serialinputport）

P3.1

TXD（serialoutputport）

P3.2

INT0（externalinterrupt0）

P3.3

INT1（externalinterrupt1）

P3.4

T0（timer0externalinput）

P3.5

T1（timer1externalinput）

Port3alsoservesthefunctionsofvariousspecialfeaturesoftheAT89C2051aslistedbelow:

1.5OscillatorCharacteristics

XTAL1andXTAL2aretheinputandoutput,respectively,ofaninvertingamplifierwhichcanbeconfiguredforuseasanon-chiposcillator,asshowninFigure1.Eitheraquartzcrystalorceramicresonatormaybeused.Todrivethedevicefromanexternalclocksource,XTAL2shouldbeleftunconnectedwhileXTAL1isdrivenasshowninFigure2.Therearenorequirementsonthedutycycleoftheexternalclocksignal,sincetheinputtotheinternalclockingcircuitryisthroughadivideby-twoflip-flop,butminimumandmaximumvoltagehighandlowtimespecificationsmustbeobserved.

1.6SpecialFunctionRegisters

Amapoftheon-chipmemoryareacalledtheSpecialFunctionRegister（SFR）spaceisshowninthetablebelow.

Notethatnotalloftheaddressesareoccupied,andunoccupiedaddressesmaynotbeimplementedonthechip.Readaccesses.totheseaddresseswillingeneralreturnrandomdata,andwriteaccesseswillhaveanindeterminateeffect.

Usersoftwareshouldnotwrite1stotheseunlistedlocations,sincetheymaybeusedinfutureproductstoinvokenewfeatures.Inthatcase,theresetorinactivevaluesofthenewbitswillalwaysbe0.

1.7RestrictionsonCertainInstructions

TheAT89C2051andisaneconomicalandcost-effectivememberofAtmel’sgrowingfamilyofmicrocontrollers.Itcontains2Kbytesofflashprogrammemory.ItisfullycompatiblewiththeMCS-51architecture,andcanbeprogrammedusingtheMCS-51instructionset.However,thereareafewconsiderationsonemustkeepinmindwhenutilizingcertaininstructionstoprogramthisdevice.

Alltheinstructionsrelatedtojumpingorbranchingshouldberestrictedsuchthatthedestinationaddressfallswithinthephysicalprogrammemoryspaceofthedevice,whichis2KfortheAT89C2051.Thisshouldbetheresponsibilityofthesoftwareprogrammer.Forexample,LJMP7E0HwouldbeavalidinstructionfortheAT89C2051（with2Kofmemory）,whereasLJMP900Hwouldnot.

1.Branchinginstructions:

LCALL,LJMP,ACALL,AJMP,SJMP,JMP@A+DPTR

Theseunconditionalbranchinginstructionswillexecutecorrectlyaslongastheprogrammerkeepsinmindthatthedestinationbranchingaddressmustfallwithinthephysicalboundariesoftheprogrammemorysize（locations00Hto7FFHforthe89C2051）.Violatingthephysicalspacelimitsmaycauseunknownprogrambehavior.

CJNE[...],DJNZ[...],JB,JNB,JC,JNC,JBC,JZ,JNZWiththeseconditionalbranchinginstructionsthesameruleaboveapplies.Again,violatingthememoryboundariesmaycauseerraticexecution.

Forapplicationsinvolvinginterruptsthenormalinterruptserviceroutineaddresslocationsofthe80C51familyarchitecturehavebeenpreserved.

2.MOVX-relatedinstructions,DataMemory:

TheAT89C2051contains128bytesofinternaldatamemory.Thus,intheAT89C2051thestackdepthislimitedto128bytes,theamountofavailableRAM.ExternalDATAmemoryaccessisnotsupportedinthisdevice,norisexternalPROGRAMmemoryexecution.Therefore,noMOVX[...]instructionsshouldbeincludedintheprogram.

Atypical80C51assemblerwillstillassembleinstructions,eveniftheyarewritteninviolationoftherestrictionsmentionedabove.Itistheresponsibilityofthecontrollerusertoknowthephysicalfeaturesandlimitationsofthedevicebeingusedandadjusttheinstructionsusedcorrespondingly.

1.8ProgramMemoryLockBits

Onthechiparetwolockbitswhichcanbeleftunprogrammed（U）orcanbeprogrammed（P）toobtaintheadditionalfeatureslistedinthetablebelow:

LockBitProtectionModes

（1）

ProgramLockBits

LB1

LB2

ProtectionType

1

U

U

Noprogramlockfeatures.

2

P

U

Furtherprogrammingofthe

Flashisdisabled.

3

P

P

Sameasmode2,alsoverify

isdisabled.

Note:

1.TheLockBitscanonlybeerasedwiththeChipEraseoperation

1.9IdleMode

Inidlemode,theCPUputsitselftosleepwhilealltheon-chipperipheralsremainactive.Themodeisinvokedbysoftware.Thecontentoftheon-chipRAMandallthespecialfunctionsregistersremainunchangedduringthismode.Theidlemodecanbeterminatedbyanyenabledinterruptorbyahardwarereset.

P1.0andP1.1shouldbesetto’0’ifnoexternalpullupsareused,orsetto’1’ifexternalpullupsareused.

Itshouldbenotedthatwhenidleisterminatedbyahardwarereset,thedevicenormallyresumesprogramexecution,fromwhereitleftoff,uptotwomachinecyclesbeforetheinternalresetalgorithmtakescontrol.On-chiphardwareinhibitsaccesstointernalRAMinthisevent,butaccesstotheportpinsisnotinhibited.ToeliminatethepossibilityofanunexpectedwritetoaportpinwhenIdleisterminatedbyreset,theinstructionfollowingtheonethatinvokesIdleshouldnotbeonethatwritestoaportpinortoexternalmemory.

1.10PowerDownMode

Inthepowerdownmodetheoscillatorisstopped,andtheinstructionthatinvokespowerdownisthelastinstructionexecuted.Theon-chipRAMandSpecialFunctionRegistersretaintheirvaluesuntilthepowerdownmodeisterminated.Theonlyexitfrompowerdownisahardwarereset.ResetredefinestheSFRsbutdoesnotchangetheon-chipRAM.TheresetshouldnotbeactivatedbeforeVCCisrestoredtoitsnormaloperatinglevelandmustbeheldactivelongenoughtoallowtheoscillatortorestartandstabilize.

P1.0andP1.1shouldbesetto’0’ifnoexternalpullupsareused,orsetto’1’ifexternalpullupsareused.

1.11ProgrammingTheFlash

TheAT89C2051isshippedwiththe2Kbytesofon-chipPEROMcodememoryarrayintheerasedstate（i.e.,contents=FFH）andreadytobeprogrammed.Thecodememoryarrayisprogrammedonebyteatatime.Oncethearrayisprogrammed,tore-programanynon-blankbyte,theentirememoryarrayneedstobeerasedelectrically.

InternalAddressCounter:

TheAT89C2051containsaninternalPEROMaddresscounterwhichisalwaysresetto000HontherisingedgeofRSTandisadvancedbyapplyingapositivegoingpulsetopinXTAL1.

ProgrammingAlgorithm:

ToprogramtheAT89C2051,thefollowingsequenceisrecommended.

1.Power-upsequence:

ApplypowerbetweenVCCandGNDpinsSetRSTandXTAL1toGND

Withallotherpinsfloating,waitforgreaterthan10milliseconds

2.SetpinRSTto’H’SetpinP3.2to’H’

3.Applytheappropriatecombinationof’H’or’L’logiclevelstopinsP3.3,P3.4,P3.5,P3.7toselectoneoftheprogrammingoperationsshowninthePEROMProgrammingModestable.

ToProgramandVerifytheArray:

4.ApplydataforCodebyteatl