东南大学计算结构CPU报告.docx
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东南大学计算结构CPU报告
ComputerOrganizationandArchitecture
COURSEDESIGN
NAME
STUDENTNUMBER
COURSE
ComputerOrganizationandArchitectureCourseDesign
PROJECT
ACentralProcessingUnit（CPU）BasingOnVerilogHDL
SOFTWAREPLATFORM
ISE14.1
DATE
APR.15.2014
1.Purpose
（1）ThepurposeofthisprojectistodesignasimpleCPU（CentralProcessingUnit）.ThisCPUhasbasicinstructionset,andwewillutilizeitsinstructionsettogenerateaverysimpleprogramtoverifyitsperformance.Forsimplicity,wewillonlyconsidertherelationshipamongtheCPU,registers,memoryandinstructionset.Thatistosayweonlyneedconsiderthefollowingitems:
Read/WriteRegisters,Read/WriteMemoryandExecutetheinstructions.
AtleastfourpartsconstituteasimpleCPU:
thecontrolunit,theinternalregisters,theALUandinstructionset,whicharethemainaspectsofourprojectdesignandwillbestudied.
（2）TheuseofISEsoftwarefordesignandsimulation.
2.Tasks
Single-addressinstructionformatisusedinoursimpleCPUdesign.Theinstructionwordcontainstwosections:
theoperationcode（opcode）,whichdefinesthefunctionofinstructions（addition,subtraction,logicoperations,etc.）;theaddresspart,inmostinstructions,theaddresspartcontainsthememorylocationofthedatumtobeoperated,wecalleditdirectaddressing.Insomeinstructions,theaddresspartistheoperand,whichiscalledimmediateaddressing.
Forsimplicity,thesizeofmemoryis256×16inthecomputer.Theinstructionwordhas16bits.Theopcodeparthas8bitsandaddressparthas8bits.TheinstructionwordformatcanbeexpressedinFigure1.
Figure1.Theinstructionformat
TheopcodeoftherelevantinstructionsarelistedinTable1.
Instruction
OPCODE
Comments
ADDX
00000001
ACC+[X]->ACC
SUBX
00000010
ACC-[X]->ACC
ANDX
00000011
ACCand[X]->ACC
ORX
00000100
ACCor[X]->ACC
NOTX
00000101
NOT[X]->ACC
SHIFTR
00000110
SHIFTACCtoRight1bit,LogicShift
SHIFTL
00000111
SHIFTACCtoLeft1bit,LogicShift
MPYX
00001000
ACC×[X]->ACC
DIVX
00001001
ACC÷[X]->ACC
JMPGEZX
00001010
IfACC≥0thenX->PCelsePC+1->PC
JMPX
00001011
X->PC
HALT
00001100
Haltaprogram
STOREX
00001101
ACC->[X]
LOADX
00001110
[X]->ACC
Table1.Listofinstructionsandrelevantopcodes
3.Theoverallconnectionexpressedinthetopmoduleform
Figure2.Theoverallconnectionexpressedinthetopmoduleform
4.InternalRegistersandMemory
4.1Memory（Dist_mem_gen_v7_1）
TheXilinxLogiCORE™IPDistributedMemoryGeneratorcoreusesXilinxSynthesisTechnology（XST）tocreateavarietyofdistributedmemories.Itgeneratesread-onlymemories（ROMs）,single,simpledual,anddual-portrandomaccessmemories（RAMs）,andSRL16-basedmemories;Supportsdatadepthsrangingfrom16–65,536words;Supportsdatawidthsrangingfrom1–1024bits.
ThismemoryisasingleportRAMgeneratedbyDist_mem_gen_v7_1.
4.2MAR（MemoryAddressRegister）
MARcontainsthememorylocationofthewordtobereadfromthememoryorwrittenintothememory.Here,READoperationisdenotedastheCPUreadsfrommemory,andWRITEoperationisdenotedastheCPUwritestomemory.Inourdesign,MARhas8bitstoaccessoneof256addressesofthememory.
4.3MBR（MemoryBufferRegister）
MBRcontainsthevaluetobestoredinmemoryorthelastvaluereadfrommemory.MBRisconnectedtotheaddresslinesofthesystembus.Inourdesign,MBRhas16bits.Themodulehasbeenhorizontallyinverted.
4.4PC（ProgramCounter）
PCkeepstrackoftheinstructionstobeusedintheprogram.Inourdesign,PChas8bits.
4.5IR（InstructionRegister）
IRcontainstheopcodepartofaninstruction.Inourdesign,IRhas8bits.
4.6ACC（Accumulator）
ACCholdsoneoperandforALU,andgenerallyACCholdsthecalculationresultofALU.Inourdesign,ACChas16bits.BRisusedasaninputofALU,itholdsotheroperandforALU.Inourdesign,BRhas16bits.Themodulehasbeenhorizontallyinverted.
4.7ALU（ArithmeticLogicUnit）
ALUisacalculationunitwhichaccomplishesbasicarithmeticandlogicoperations.Inourdesign,someoperationsmustbesupportedwhicharelistedasfollows:
Table2.ALUOperations
4.8CU（MicroprogrammedControlUnit）
WehavelearnttheknowledgeofMicroprogrammedcontrolunit.Here,weonlyreviewsometermsandbasicstructures.
IntheMicroprogrammedcontrol,themicroprogramconsistsofsomemicroinstructionsandthemicroprogramisstoredincontrolmemorythatgeneratesallthecontrolsignalsrequiredtoexecutetheinstructionsetcorrectly.Themicroinstructioncontainssomemicro-operationswhichareexecutedatthesametime.
Figure3showsthekeyelementsofsuchanimplementation.Thesetofmicroinstructionsisstoredinthecontrolmemory.Thecontroladdressregistercontainstheaddressofthenextmicroinstructionstoberead.Whenamicroinstructionisreadfromthecontrolmemory,itistransferredtoacontrolbufferregister.Theregisterconnectstothecontrollinesemanatingfromthecontrolunit.Thus,readingamicroinstructionfromthecontrolmemoryisthesameasexecutingthatmicroinstruction.Thethirdelementshowninthefigureisasequencingunitthatloadsthecontroladdressregisterandissuesareadcommand.
Figure3.ControlUnitMicro-architecture
Inmydesign,IsimplifythestructureofMU.Figure4showstheControlUnitMicro-architectureinmydesign.CMisaDistributedROMgeneratedbyDist_mem_gen_v7_1.Itsfunctionisthesamewiththecontrolmemoryplusthecontrolbufferregisterinfigure3.Similarly,theSequencingLogic’sfunctionisthesamewithsequencinglogicpluscontroladdressregisterinfigure3.
Figure4.ControlUnitMicro-architectureinmydesign
ControlSignals
CM地址控制
C0
CAR<=CAR+1
C1
CAR<=***
C2
CAR<=0
系统总线
C3
RWmemory
C5
Wmemory
数据通路
C4
memory<=MBR
C6
MBR<=memory
C7
IR<=MBR[15..8]
C8
MAR<=MBR[7..0]
C9
BR<=MBR
C10
PC<=MBR
C11
MAR<=PC
C12
PC<=PC+1
C13
ALU<=BR
C14
ALU<=ACC
C15
ACC<=ALU
C16
ACC<=BR
C17
MBR<=ACC
ALU控制
ALU0
ALU1
ALU2
ALU3
Table3.Meaningsofeachbitofcontrolsignal
运算
ALU[3：
0]
ADD
0001
SUBX
0010
ANDX
0011
ORX
0100
NOTX
0101
SHIFTR
0110
SHIFTL
0111
MPYX
1000
DIVX
1001
Table4.MeaningsofALU[3：
0]signal
Table5.CPUinstructionsetandrelevantmicro-operationsandcontrolsignals
Asfigure4andtable3shows,thereare2outputbusfromControlUnit.OneisthecontrolsignalbusCS[17：
0],theotheroneistheALUFlagsignalbusALUFlag[3：
0],whichindicatesthatwhichcalculationisgoingtobeexecutedinALU.Morespecifically,table4showsmeaningsofALU[3：
0]signal.
Table5showstheCPUinstructionsetandaccordinglymicro-operationsandcontrolsignals.Thisisthefoundationofthewholedesign.
5.Designdescriptionofthesimulationinputwaveforms
Twosimulationinputsignalsareneededinmydesign.
（1）clk:
clocksignalofthewholesystem.Theclockperiodis10us.Alltheregistersarepositive-edge-triggered.
（2）reset:
resetwhenreset=1.Alltheresetsignalsfortheregistersaresynchronizedtotheclocksignal.
6.Simulationresults
（1）1+2+3+……+100=5050
Table6.Programof1+2+3+……+100
Figure5.Waveformof1+2+3+……+100
（2）12×3=36
Table7.Programof12×3
Figure6.Waveformof12×3
（3）12÷3=4
Table8.Programof12÷3
Figure7.Waveformof12÷3
7.ConclusionsandDiscussions
（1）Ittakes46mstofinishthecalculation1+2+3+……+100=5050,intheconditionoftheclockperiod10us.
（2）Theresultofthemultiplicationcalculationhasbeenlimitedto8bitsincetheMRregisterisnotused.
（3）Thedivisioncalculationcanonlybeencalledexactdivision,sincetheoperatorwhichisusedinthecodeis“/”.
（4）感想：
CPU的设计相对比较复杂，在真正用ISE进行编程仿真之前需要把课本上CPU部分尤其是CU的工作原理弄清楚，并用EXCEL工具设计自己的指令集和其对应的微操作。
这中间很多地方容易出错，也容易使人迷糊，这时就要勤于动手在纸上规划自己的设计。
当草稿纸上和EXCEL中的设计完成后，再用ISE进行编程仿真就会很快了，良好的设计会对后面的工作起到很大的促进作用。
在这中间会对课本知识有更加透彻深入的理解。
这个实验完全由我独立完成，其中前期设计所使用的时间占到了总花费时间的一半，后期编程调试仿真花费了总时间的另一半。
Appendix
----------MAR----------
moduleMAR（
input[15:
0]MBRdata,
input[7:
0]PCdata,
input[17:
0]CS,
output[7:
0]MA
）;
reg[7:
0]MA;
always@（posedgeCS[8]orposedgeCS[11]）
begin
if（CS[8]==1）beginMA<=MBRdata[7:
0];end
if（CS[11]==1）beginMA<=PCdata;end
end
endmodule
----------MBR----------
moduleMBR（
output[15:
0]MBdata,
input[17:
0]CS,
input[15:
0]ACC,
input[15:
0]MEM
）;
reg[15:
0]MBdata;
always@（posedgeCS[6]orposedgeCS[17]）
begin
if（CS[6]==1）beginMBdata<=MEM;end
if（CS[17]==1）beginMBdata<=ACC;end
end
endmodule
-----------PC----------
modulePC（
inputreset,
input[17:
0]CS,
input[15:
0]MBRdata,
inputclk,
output[7:
0]PCdata
）;
reg[7:
0]PCdata;
always@（posedgeclk）
begin
if（reset==1）beginPCdata<=8'b00000000;end
if（CS[10]==1）beginPCdata<=MBRdata[7:
0];end
if（CS[12]==1）beginPCdata<=PCdata+1;end
end
endmodule
----------IR----------
moduleIR（
input[17:
0]CS,
input[15:
0]MBRdata,
output[7:
0]IRdata
）;
reg[7:
0]IRdata;
always@（posedgeCS[7]）
begin
if（CS[7]==1）beginIRdata<=MBRdata[15:
8];end
end
endmodule
----------ACC----------
moduleACC（
input[17:
0]CS,
input[15:
0]ALUdata,
input[15:
0]BRdata,
inputreset,
inputclk,
output[15:
0]ACCdata,
outputzflag
）;
reg[15:
0]ACCdata;
regzflag;
always@（posedgeclk）
begin
if（reset==1）
begin
ACCdata<=16'b0000000000000000;
zflag<=1;
end
elseif（ACCdata[15]==0）
begin
if（CS[15]==1）
begin
ACCdata<=ALUdata;
zflag<=1;
end
elseif（CS[16]==1）
begin
ACCdata<=BRdata;
zflag<=1;
end
elsebeginzflag<=1;end
end
else
begin
if（CS[15]==1）
begin
ACCdata<=ALUdata;
z
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