Laser Thermal Annealing Enabling ultralow thermal budget processes.docx

Laser Thermal Annealing Enabling ultralow thermal budget processes.docx

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LaserThermalAnnealingEnablingultralowthermalbudgetprocesses

LaserThermalAnnealing:

Enablingultra-lowthermalbudgetprocessesfor3Djunctionsformationanddevices

Annealingof3Darchitecturesisoneofthemajorchallengesforcurrentandnextgenerationdevicesforvariousapplicationsrangingfromsensors,microprocessorsorhighdensitymemories.OneofthemostpromisingsolutionsisLaserThermalAnnealing（LTA）,anultrafastandlowthermalbudgetprocessalreadyadoptedinproductionforpassivationofBackSideIlluminatedCMOSImagingSensors（CIS）andPowerDiodesandTransistors（IGBT）.Thehightemperatureannealingrequired（>;1400°C）needstoberestrainedtoverythinlayerswhilekeepinglowtemperatureofunderlyingfragilelayersanddevices.Toachievethat,oneneedstouseauniqueultrafastannealingduration（subμsec）andaproperLaserwavelength.Thisenablestoreachmetastablethermalprocesses,locking-intheelectricalsurfacepropertiesofthesemiconductorwhilenotdamagingburieddevices.Wepresentareviewofthosenewprocessesincludingrecentdevelopmentinemergingmemoryapplicationswhere3Dverticalstackoffunctionallayersofdevicesisrealized.

Thispaperappearsin:

JunctionTechnology（IWJT）,201212thInternationalWorkshopon,IssueDate:

14-15May2012,Writtenby:

Venturini,Julien

©2012IEEE

Introduction

The“MorethanMoore”lawdriving3Dintegrationofdevicesisshapedbytwomajorkeyrequirements:

Firstly,theneedtoreachhigherintrinsicdeviceperformancesbydesigningverticallydiscreteorintegrateddevices;secondlytheneedtomanagemoreinformationflowintimeandspace,wherereducingplanardevicesizeislimitedbyphysicalandcostbarriersconsequentlydrivingtheneedtostackdevicelayersvertically.Forthosetwobasicrequirementsthedimensionsof3Dstructureatstaketypicallyrangefromfewnmto10thofμm .Manufacturingofthosestructuresusingstandardorexistingmanufacturingprocessflowsleadstoroadblocksforthermalorotherprocessincompatibilitiesreasons,orincreasessignificantlyandnonlinearlymanufacturingcost.Thosechallengesareevenharsherwhenonehastodealwithintegratinganincreasednumberofmaterialsfromtheperiodictableandwithincreasedcomplexityinthedesignanddevicestructure.Overcomingthosechallengespushesdevicemanufacturerstoexploreandstudydifferentdesignandprocessflowswhicharenotalldoomedtosuccess.

Moreparticularly,concerningthespecificthermalprocessintegrationchallenge,oneneedstoavoiddamaginglayersalreadymanufacturedunderneath,whichtranslatesintocontrollingverticallythetemperaturegradientandthetotalthermalbudgetateachannealingstep.Subpsec “timeattemperature”isamustwhenonewantstoreachsuchpm scaletemperaturegradient.Secondly,tocoupleefficientlythelaserlightwiththematerialunderneath,oneneedstoannealselectivelythemateriallayersin2D.Lastbutnotleast,tomaximizemanufacturingyieldonerequiresannealingveryuniformlyanareatothescaleofatleastadevice/die.Ageneraltrendofnewannealingtoolspecificationrequirementsissummarizedinfigure1.

Pulsedlaserannealingtechnologiesaretodaytheonlyoneabletoanswertothoseneeds.OneofthemostpromisingsolutionalreadyimplementedinproductioninSemiconductorFabsisLaserThermalAnnealing（LTA）,anultrafastandlowthermalbudgetprocessinthesubμsec range.

Figure1Semiconductorindustrytrendsandthermalprocessequipmentimplications

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AftershowingthemainassetsandspecificationsofLTAtechnology,wepresenttheLTAprocessforthecontactformationstepofPowerTransistors（IGBT）andforthepassivationstepofBackSideIlluminatedCMOSImagingSensors（BSI-CIS）.Wealsopresentrecentdevelopmentsinverticallystackedfunctionallayersofdeviceincreasingthedensityperunitareaofmemories.Whilethetwofirstapplicationsarecallingthecapabilitytothindownwafersandformthedeviceitselfintheverticalbulkofthewaferattheμm range,thememoryapplicationdealswithnmrangelayerprocesses.Inallcases,thehightemperatureannealing（>1400°C）needstoberestrainedtoverythinlayerswhilekeepinglowtemperature（<300°C）ofunderlyingdevicelayersincludingfragilemetalsorbondinglayers.Additionally,tooptimizesuchultrafastannealingprocesses,itisrequiredtopredictadequatelythetemperaturegradientinthestackbyusingsophisticatedsimulationtoolsnotyetavailableinTCADtool.Someofthosesimulationcalculationswillalsobepresentedinthefirstsectionofthispaper.

∙

o1.Introduction

o2.TheLTAtechnology

o3.LTAprocessforbacksidepassivationofthinnedwafers

o4.3DMemories-PINDiodeLTAprocess

o5.ConclusionsandSummary

SECTION2.

TheLTAtechnology

Whenonewantstoannealwithapulsedlasertoreach2Dand3Dspatialprocessselectivityandhighprocessuniformity,asseeninfigure1,thewavelengthandthepulsedurationarethemainlasermetricstobecontrolledandadjustedwhileauniquelaserbeamisrequiredtoannealasingledieinasingleshot.

 A-LaserWavelength

Forthewavelength,thefigure2showstheabsorptiondepthinsiliconofdifferenttypicalindustriallaserwavelength.Weseethatinordertoreachtheproperselectivitytoenableprocessesatthenanometerscale,theUVwavelengthspectrumisrequired.

Figure2Absorptiondepthversuslaserwavelengthincrystallinesilicon

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 B-PulseDuration

Concerningthepulseduration,simulationsarerequiredtopredictthemeltandrecrystallizationaswellasthetemperaturedynamics.Beingultrafastisessentialwhileonesneedstocarenotreachingdegreeofsuperheatingwhichwoulddamagethelayertobeannealedorwouldnotallowaproperanddefect-lessrecrystallization.Acomparisonof2differentpulsedurationdynamicsisshownonfigure3for308nmExcimerlasers.Onecanwitnessthatsuperheatingoftheliquidphaseisoccurringinthecaseofthe25nspulse,leadingtocrystallizationvelocitiesliabletoleavealargernumberofdefect[1].Atradeoffisclearlyappearinginthe100to300nsdurationinordertobothreachametastableadiabaticregimeenablinghighactivationofdopantsandathermaldynamicavoidingsurfacedamageanddefectgeneration.

Figure3Simulationshowingthetemperaturedynamicatthesiliconsurfacewith2differentpulsedurationat308nmwavelength.Laserenergydensitiesareadjustedtoreacha50nmjunctionformation

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Simulationofthetemperaturegradientinthedepthofthesiliconisshowninfigure4.InthisexampleofatypicalBSI-CISstructure,thetemperatureintheburiedmetallinesarebelowdamagethresholdwhilesurfacetemperatureisreachingmeltingphasetoformanultra-shallowjunction.

Figure4Temperatureverticalgradientina3DBSI-CISstructure

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 C-Processuniformity-theFullDeviceExposure（FDE）technology

Inordertofulfilltherequirementsforauniformprocess,theshotareahastobechangedaccordingtothedevicegeometry.Asshownpreviouslyusingmicro-scalesheetresistancemeasurements[2],thepresenceoftheshotborderoroverlapwithintheareaofinterestmayinducesignificantnon-uniformitiesinjunctionproperties.Sincethejunctionproperties（thickness,activationrate）mayinfluencecarrierrecombination,theyshouldbecarefullycontrolled.Figure5showsanexampleoftheinfluenceofthelaserbeamoverlaponsensordevices.

Figure5SensorsignalintensityprofilesusingLTAwith（solidline）andwithout（dashedline）overlapinthesensorarea

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Asaconsequence,thedeviceshouldbeannealedwithinaSingleShotArea（SSA）.ThisSSAisdefinedastheareawhichisguaranteedtobeirradiatedwithinthetophatofthelaserbeam（Fig.6）andonlyonce,takingalsointoaccountwithinwaferandwafertowaferpositioningaccuracy.TheSSAisthuscalculatedasafunctionofthedevicegeometry.

Figure6Asnapshotofa5.6×7.9 mm rectanglelaserbeamshowinguniformityoverthedeviceinthexandydirection

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Anexampleofa-Siwafersannealedwitha13×16mm 2  fieldofexposureisshowninfigure7.Atlaserenergydensitiescorrespondingtothetophatareaofthebeam,shot-to-shotdistancesareclosetotypicalscribelinewidths.Thus,largedevicescanbeprocesswithsuchasystem.Itistobenotedthatwithsuchlargesizes,dependingondevicedesign,oneorseveraldiescouldbeannealedwithineachSSA,thusoptimizingthethroughputofthesystem.

Figure7Shotmapona-SiwaferforarectangularSingleShotArea（SSA）of13×16 mm 2  

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Otherstrategiestoachieveuniformityfordeviceslargerthanthemaximumequipmentfieldofexposurearealsoexplored[2]–[3]andshowninfigure8.Thisconsistforinstancetoplaywithmultipleshotsandoverlapratiobetweentwoadjacentlaserpulsesoverasingledevice.Thisapproachisobviouslymoreadaptedtolowthroughputmanufacturingandhighaddedvaluelargeareadevices.Figure8showstheeffectofmultiplepulseandoverlaprationadjustmentforagivenbeamgeometry.

Figure8.Junctionprocessuniformityfromμscale sheetresistance（20 μm stepR s  scansintheoverlapregion）with1pulse（triangles）and3pulses（circles）.[2]

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∙

o1.Introduction

o2.TheLTAtechnology

o3.LTAprocessforbacksidepassivationofthinnedwafers

o4.3DMemories-PINDiodeLTAprocess

o5.ConclusionsandSummary

SECTION3.

LTAprocessforbacksidepassivationofthinnedwafers

 A-Discretepo