INSTD_LOGIC;
DATA:
INSTD_LOGIC_VECTOR<3DOWNTO0>;--4位预置数
DOUT:
OUTSTD_LOGIC_VECTOR<3DOWNTO0>;--计数值输出
COUT:
OUTSTD_LOGIC>;--计数进位输出
ENDT12;
ARCHITECTUREbehavOFT12IS
SIGNALQ:
STD_LOGIC_VECTOR<3DOWNTO0>;
BEGIN
REG:
PROCESS
BEGIN
IFLOAD='0'THENQ<=DATA;--允许加载
ELSIFCLK'EVENTANDCLK='1'THEN--检测时钟上升沿
IFRST='0'THENQ<='0'>;--计数器异步复位
ELSE
IFEN='1'THEN--检测是否允许计数或加载〔同步使能〕
IFLOAD='0'THENQ<=DATA;--允许加载
ELSE
IFQ<12THENQ<=Q+1;--允许计数,检测是否小于9
ELSEQ<='0'>;--大于等于9时,计数值清零
ENDIF;
ENDIF;
ENDIF;
ENDIF;
ENDIF;
ENDPROCESS;
:
PROCESS
BEGIN
IFQ=12THENCOUT<='1';--计数大于9,输出进位信号
ELSECOUT<='0';
ENDIF;
DOUT<=Q;--将计数值向端口输出
ENDPROCESS;
ENDbehav;
3-5设计含有异步清零和计数使能的16位二进制加减可控计数器.
--解:
用VHDL实现含有异步清零和计数使能的16位二进制加减可控计数器.
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
USEIEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITYADD_SUB_16IS
PORTINSTD_LOGIC;
CQ:
OUTSTD_LOGIC_VECTOR<15DOWNTO0>;
COUT:
OUTSTD_LOGIC>;
ENDENTITYADD_SUB_16;
ARCHITECTUREA_S_16OFADD_SUB_16IS
BEGIN
PROCESS
VARIABLECQI:
STD_LOGIC_VECTOR<15DOWNTO0>;
BEGIN
IFRST='1'THENCQI:
='0'>;--计数器异步复位
ELSIFCLK'EVENTANDCLK='1'THEN--检测时钟上升沿
IFADD_EN='1'THEN--检测是否允许计数<同步他能>
IFCQI<16#FFFF#THENCQI:
=CQI+1;--允许计数,检测是否小于65535
ELSECQI:
='0'>;--大于65535,计数值清零
ENDIF;
IFCQI=16#FFFF#THENCOUT<='1';--计数大于9,输出进位信号
ELSECOUT<='0';
ENDIF;
ENDIF;
IFSUB_EN='1'THEN--检测是否允许计数<同步他能>
IFCQI>0THENCQI:
=CQI-1;--允许计数,检测是否小于65535
ELSECQI:
='1'>;--大于65535,计数值清零
ENDIF;
IFCQI=0THENCOUT<='1';--计数大于9,输出进位信号
ELSECOUT<='0';
ENDIF;
ENDIF;
ENDIF;
CQ<=CQI;--将计数值向端口输出
ENDPROCESS;
ENDARCHITECTUREA_S_16;
3-6图3-18是一个含有上升沿触发的D触发器的时序电路,试写出此电路的VHDL设计文件.
图3-18时序电路
--解:
实现图4-19电路的VHDL程序t4_19.vhd
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
ENTITYt4_19IS
PORTINSTD_LOGIC;
OUT1:
OUTSTD_LOGIC>;
ENDENTITYt4_19;
ARCHITECTUREsxdlOFt4_19IS----时序电路sxdl
SIGNALQ:
STD_LOGIC;
BEGIN
PROCESS
BEGIN
IFCLK0'EVENTANDCLK0='1'THEN--检测时钟上升沿
Q<=NOT;
ENDIF;
ENDPROCESS;
OUT1<=NOTQ;
ENDARCHITECTUREsxdl;
3-7给出1位全减器的VHDL描述;最终实现8位全减器.要求:
1>首先设计1位半减器,然后用例化语句将它们连接起来,图4-20中h_suber是半减器,diff是输出差,s_out是借位输出,sub_in是借位输入.c
yin
xin
diff_out
b
a
图3-191位全加器
--解<1.1>:
实现1位半减器h_suber
LIBRARYIEEE;--半减器描述<1>:
布尔方程描述方法
USEIEEE.STD_LOGIC_1164.ALL;
ENTITYh_suberIS
PORTINSTD_LOGIC;
diff,s_out:
OUTSTD_LOGIC>;
ENDENTITYh_suber;
ARCHITECTUREhs1OFh_suberIS
BEGIN
Diff<=xXOR;
s_out<=ANDy;
ENDARCHITECTUREhs1;
--解<1.2>:
采用例化实现图4-20的1位全减器
LIBRARYIEEE;--1位二进制全减器顺层设计描述
USEIEEE.STD_LOGIC_1164.ALL;
ENTITYf_suberIS
PORTINSTD_LOGIC;
sub_out,diff_out:
OUTSTD_LOGIC>;
ENDENTITYf_suber;
ARCHITECTUREfs1OFf_suberIS
PONENTh_suber--调用半减器声明语句
PORTINSTD_LOGIC;
diff,s_out:
OUTSTD_LOGIC>;
ENDPONENT;
SIGNALa,b,c:
STD_LOGIC;--定义1个信号作为内部的连接线.
BEGIN
u1:
h_suberPORTMAPxin,y=>yin,diff=>a,s_out=>b>;
u2:
h_suberPORTMAPa,y=>sub_in,diff=>diff_out,s_out=>c>;
sub_out<=cORb;
ENDARCHITECTUREfs1;
<2>以1位全减器为基本硬件,构成串行借位的8位减法器,要求用例化语句来完成此项设计<减法运算是x-y-sun_in=difft>.
xinsub_out
yinu0
sub_indiff_out
x0
y0
sin
diff0
xinsub_out
yinu1
sub_indiff_out
x1
y1
diff1
xinsub_out
yinu7
sub_indiff_out
x7
y7
sout
diff7
……………….
……………….
串行借位的8位减法器
a0
a1
a6
--解<2>:
采用例化方法,以1位全减器为基本硬件;实现串行借位的8位减法器<上图所示>.
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
ENTITYsuber_8IS
PORTINSTD_LOGIC;
y0,y1,y2,y3,y4,y5,y6,y7,sin:
INSTD_LOGIC;
diff0,diff1,diff2,diff3:
OUTSTD_LOGIC;
diff4,diff5,diff6,diff7,sout:
OUTSTD_LOGIC>;
ENDENTITYsuber_8;
ARCHITECTUREs8OFsuber_8IS
PONENTf_suber--调用全减器声明语句
PORTINSTD_LOGIC;
sub_out,diff_out:
OUTSTD_LOGIC>;
ENDPONENT;
SIGNALa0,a1,a2,a3,a4,a5,a6:
STD_LOGIC;--定义1个信号作为内部的连接线.
BEGIN
u0:
f_suberPORTMAPx0,yin=>y0,diff_out=>diff0,sub_in=>sin,sub_out=>a0>;
u1:
f_suberPORTMAPx1,yin=>y1,diff_out=>diff1,sub_in=>a0,sub_out=>a1>;
u2:
f_suberPORTMAPx2,yin=>y2,diff_out=>diff2,sub_in=>a1,sub_out=>a2>;
u3:
f_suberPORTMAPx3,yin=>y3,diff_out=>diff3,sub_in=>a2,sub_out=>a3>;
u4:
f_suberPORTMAPx4,yin=>y4,diff_out=>diff4,sub_in=>a3,sub_out=>a4>;
u5:
f_suberPORTMAPx5,yin=>y5,diff_out=>diff5,sub_in=>a4,sub_out=>a5>;
u6:
f_suberPORTMAPx6,yin=>y6,diff_out=>diff6,sub_in=>a5,sub_out=>a6>;
u7:
f_suberPORTMAPx7,yin=>y7,diff_out=>diff7,sub_in=>a6,sub_out=>sout>;
ENDARCHITECTUREs8;
3-8给出一个4选1多路选择器的VHDL描述.选通控制端有四个输入:
S0、S1、S2、S3.当且仅当S0=0时:
Y=A;S1=0时:
Y=B;S2=0时:
Y=C;S3=0时:
Y=D.
--解:
4选1多路选择器VHDL程序设计.
LIBRARYIEEE;--图3-20RTL图的VHDL程序顶层设计描述
USEIEEE.STD_LOGIC_1164.ALL;
ENTITYmux41aIS
PORTINSTD_LOGIC;
S0,S1,S2,S3:
INSTD_LOGIC;
Y:
OUTSTD_LOGIC>;
ENDENTITYmux41a;
ARCHITECTUREoneOFmux41aIS
SIGNALS