TMS320x2833x Multichannel Buffered Serial Port McBSP Reference Guide第七章 外文.docx

TMS320x2833x Multichannel Buffered Serial Port McBSP Reference Guide第七章 外文.docx

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TMS320x2833xMultichannelBufferedSerialPortMcBSPReferenceGuide第七章外文

第7章ReceiverConfiguration

ToconfiguretheMcBSPreceiver,performthefollowingprocedure:

1.PlacetheMcBSP/receiverinreset（seeSection7.2）.

2.ProgramMcBSPregistersforthedesiredreceiveroperation（seeSection7.1）.

3.Takethereceiveroutofreset（seeSection7.2）.

7.1ProgrammingtheMcBSPRegistersfortheDesiredReceiverOperation

ThefollowingisalistofimportanttaskstobeperformedwhenyouareconfiguringtheMcBSPreceiver.EachtaskcorrespondstooneormoreMcBSPregisterbitfields.

•Globalbehavior:

1、SetthereceiverpinstooperateasMcBSPpins.

2、Enable/disablethedigitalloopbackmode.

3、Enable/disabletheclockstopmode.

4、Enable/disablethereceivemultichannelselectionmode.

•Databehavior:

1、Choose1or2phasesforthereceiveframe.

2、Setthereceivewordlength（s）.

3、Setthereceiveframelength.

4、Enable/disablethereceiveframe-synchronizationignorefunction.

5、Setthereceivecompandingmode.

6、Setthereceivedatadelay.

7、Setthereceivesign-extensionandjustificationmode.

8、Setthereceiveinterruptmode.

•Frame-synchronizationbehavior:

1、Setthereceiveframe-synchronizationmode.

2、Setthereceiveframe-synchronizationpolarity.

3、Setthesamplerategenerator（SRG）frame-synchronizationperiodandpulsewidth.

•Clockbehavior:

1、Setthereceiveclockmode.

2、Setthereceiveclockpolarity.

3、SettheSRGclockdivide-downvalue.

4、SettheSRGclocksynchronizationmode.

5、SettheSRGclockmode（chooseaninputclock）.

7.2ResettingandEnablingtheReceiver

Thefirststepofthereceiverconfigurationprocedureistoresetthereceiver,andthelaststepistoenablethereceiver（totakeitoutofreset）.Table7-1describesthebitsusedforbothofthesesteps.

7.2.1ResetConsiderations

Theserialportcanberesetinthefollowingtwoways:

1.TheDSPreset（XRSsignaldrivenlow）placesthereceiver,transmitter,andsamplerategeneratorinreset.Whenthedeviceresetisremoved（XRSsignalreleased）,GRST=FRST=RRST=XRST=0keeptheentireserialportintheresetstate.

2.TheserialporttransmitterandreceivercanberesetdirectlyusingtheRRSTandXRSTbitsintheserialportcontrolregisters.ThesamplerategeneratorcanberesetdirectlyusingtheGRSTbitinSPCR2.

Table7-2showsthestateofMcBSPpinswhentheserialportisresetduetoadeviceresetandadirectreceiver/transmitterreset.

FormoredetailsaboutMcBSPresetconditionsandeffects,seeSection9.2,ResettingandInitializingaMcBSP.

7.3SettheReceiverPinstoOperateasMcBSPPins

ToconfigureapinforitsMcBSPfunction,youshouldconfigurethebitsoftheGPxMUXnregisterappropriately.Inadditiontothis,bits12and13ofthePCRregistermustbesetto0.Thesebitsaredefinedasreserved.

7.4Enable/DisabletheDigitalLoopbackMode

TheDLBbitdetermineswhetherthedigitalloopbackmodeison.DLBisdescribedinTable7-3.

7.4.1DigitalLoopbackMode

Inthedigitalloopbackmode,thereceivesignalsareconnectedinternallythroughmultiplexerstothecorrespondingtransmitsignals,asshowninTable7-4.ThismodeallowstestingofserialportcodewithasingleDSPdevice;theMcBSPreceivesthedataittransmits.

Table7-4.ReceiveSignalsConnectedtoTransmitSignalsinDigitalLoopbackMode

7.5Enable/DisabletheClockStopMode

TheCLKSTPbitsdeterminewhethertheclockstopmodeison.CLKSTPisdescribedinTable7-5.

Table7-5.RegisterBitsUsedtoEnable/DisabletheClockStopMode

7.5.1ClockStopMode

TheclockstopmodesupportstheSPImaster-slaveprotocol.IfyoudonotplantousetheSPIprotocol,youcanclearCLKSTPtodisabletheclockstopmode.

Intheclockstopmode,theclockstopsattheendofeachdatatransfer.Atthebeginningofeachdatatransfer,theclockstartsimmediately（CLKSTP=10b）orafterahalf-cycledelay（CLKSTP=11b）.TheCLKXPbitdetermineswhetherthestartingedgeoftheclockontheMCLKXpinisrisingorfalling.TheCLKRPbitdetermineswhetherreceivedataissampledontherisingorfallingedgeoftheclockshownontheMCLKRpin.

Table7-6summarizestheimpactofCLKSTP,CLKXP,andCLKRPonserialportoperation.Intheclockstopmode,thereceiveclockistiedinternallytothetransmitclock,andthereceiveframe-synchronizationsignalistiedinternallytothetransmitframe-synchronizationsignal.

Table7-6.EffectsofCLKSTP,CLKXP,andCLKRPontheClockScheme

7.6Enable/DisabletheReceiveMultichannelSelectionMode

TheRMCMbitdetermineswhetherthereceivemultichannelselectionmodeison.RMCMisdescribedinTable7-7.Formoredetails,seeSection5.6,ReceiveMultichannelSelectionMode.

Table7-7.RegisterBitUsedtoEnable/DisabletheReceiveMultichannel

7.7ChooseOneorTwoPhasesfortheReceiveFrame

TheRPHASEbit（seeTable7-8）determineswhetherthereceivedataframehasoneortwophases.

Table7-8.RegisterBitUsedtoChooseOneorTwoPhasesfortheReceiveFrame

7.8SettheReceiveWordLength（s）

TheRWDLEN1andRWDLEN2bitfields（seeTable7-9）determinehowmanybitsareineachserialwordinphase1andinphase2,respectively,ofthereceivedataframe.

Table7-9.RegisterBitsUsedtoSettheReceiveWordLength（s）

7.8.1WordLengthBits

Eachframecanhaveoneortwophases,dependingonthevaluethatyouloadintotheRPHASEbit.Ifasingle-phaseframeisselected,RWDLEN1selectsthelengthforeveryserialwordreceivedintheframe.Ifadual-phaseframeisselected,RWDLEN1determinesthelengthoftheserialwordsinphase1oftheframeandRWDLEN2determinesthewordlengthinphase2oftheframe.

7.9SettheReceiveFrameLength

TheRFRLEN1andRFRLEN2bitfields（seeTable7-10）determinehowmanyserialwordsareinphase1andinphase2,respectively,ofthereceivedataframe.

7.9.1SelectedFrameLength

Thereceiveframelengthisthenumberofserialwordsinthereceiveframe.Eachframecanhaveoneortwophases,dependingonvaluethatyouloadintotheRPHASEbit.

Ifasingle-phaseframeisselected（RPHASE=0）,theframelengthisequaltothelengthofphase1.Ifadual-phaseframeisselected（RPHASE=1）,theframelengthisthelengthofphase1plusthelengthofphase2.

The7-bitRFRLENfieldsallowupto128wordsperphase.SeeTable7-11forasummaryofhowtocalculatetheframelength.Thislengthcorrespondstothenumberofwordsorlogicaltimeslotsorchannelsperframe-synchronizationpulse.

ProgramtheRFRLENfieldswith[wminus1],wherewrepresentsthenumberofwordsperphase.Fortheexample,ifyouwantaphaselengthof128wordsinphase1,load127intoRFRLEN1.

7.10Enable/DisabletheReceiveFrame-SynchronizationIgnoreFunction

TheRFIGbit（seeTable7-12）controlsthereceiveframe-synchronizationignorefunction.

7.10.1UnexpectedFrame-SynchronizationPulsesandtheFrame-SynchronizationIgnoreFunction

Ifaframe-synchronizationpulsestartsthetransferofanewframebeforethecurrentframeisfullyreceived,thispulseistreatedasanunexpectedframe-synchronizationpulse.WhenRFIG=1,receptioncontinues,ignoringtheunexpectedframe-synchronizationpulses.

WhenRFIG=0,anunexpectedFSRpulsecausestheMcBSPtodiscardthecontentsofRSR[1,2]infavorofthenewincomingdata.Therefore,ifRFIG=0andanunexpectedframe-synchronizationpulseoccurs,theserialport:

1.Abortsthecurrentdatatransfer

2.SetsRSYNCERRinSPCR1to1

3.Beginsthetransferofanewdataword

Formoredetailsabouttheframe-synchronizationerrorcondition,seeSection4.3,UnexpectedReceiveFrame-SynchronizationPulse.

7.10.2ExamplesofEffectsofRFIG

Figure7-1showsanexampleinwhichwordBisinterruptedbyanunexpectedframe-synchronizationpulsewhen（R/X）FIG=0.Inthecaseofreception,thereceptionofBisaborted（Bislost）,andanewdatawordinthisexample）isreceivedaftertheappropriatedatadelay.Thisconditionisareceivesynchronizationerror,whichsetstheRSYNCERRbit.

Figure7-1.UnexpectedFrame-SynchronizationPulseWith（R/X）FIG=0

IncontrastwithFigure7-1,Figure7-2showsMcBSPoperationwhenunexpectedframe-synchronizationsignalsareignored（when（R/X）FIG=1）.Here,thetransferofwordBisnotaffectedbyanunexpectedpulse.

Figure7-2.UnexpectedFrame-SynchronizationPulseWith（R/X）FIG=1

7.11SettheReceiveCompandingMode

TheRCOMPANDbits（seeTable7-13）determinewhethercompandingoranotherdatatransferoptionischosenforMcBSPreception.

Table7-13.RegisterBitsUsedtoSettheReceiveCompandingMode（continued）

7.11.1Companding

Companding（COMpressingandexPANDing）hardwareallowscompressionandexpansionofdataineitherµ-laworA-lawformat.ThecompandingstandardemployedintheUnitedStatesandJapanisµ-law.TheEuropeancompandingstandardisreferredtoasA-law.Thespecificationsforµ-lawandA-lawlogPCMarepartoftheCCITTG.711recommendation.

A-lawandµ-lawallow13bitsand14bitsofdynamicrange,respectively.Anyvaluesoutsidethisrangearesettothemostpositiveormostnegativevalue.Thus,forcompandingtoworkbest,thedatatransferredtoandfromtheMcBSPviatheCPUorDMAcontrollermustbeatleast16bitswide.

Theµ-lawandA-lawformatsbothencodedatainto8-bitcodewords.Compandeddataisalways8bitswide;theappropriatewordlengthbits（RWDLEN1,RWDLEN2,XWDLEN1,XWDLEN2）mustthereforebesetto0,indicatingan8-bitwideserialdatastream.Ifcompandingisenabledandeitheroftheframephasesdoesnothavean