128入128出的tst接线器DOC.docx
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128入128出的tst接线器DOC
通信集成电路实验报告
128入128出的tst接线器
128入128出的tst接线器
T-S-T交换网络是由输入级T接线器(TA)和输出级T接线器(TB),中间接有S型时分接线器组成,
T模块包括16个T8接线器,T输入同样调用了16次,在S接线器在总的模块调用,实现了数据信息的传输。
S接线器将数据放入16个寄存器中,通过输出得到控制。
程序
modulec_b(clk,rst,data_in,data_out);
inputclk,rst;
inputdata_in;
output[7:
0]data_out;
reg[2:
0]num;
reg[7:
0]data_out;
always@(posedgeclk)
if(rst)
begin
data_out=8'b0000_0000;
num=3'b000;
end
else
begin
data_out={data_out[6:
0],data_in};
num=num+1;
end
endmodule
modulemux(out,hw0,hw1,hw2,hw3,hw4,hw5,hw6,hw7,sel);
output[7:
0]out;
input[7:
0]hw0,hw1,hw2,hw3,hw4,hw5,hw6,hw7;
input[2:
0]sel;
reg[7:
0]out;
always@(hw0orhw1orhw2orhw3orhw4orhw5orhw6orhw7orsel)
begin
case(sel)
3'b000:
out=hw0;
3'b001:
out=hw1;
3'b010:
out=hw2;
3'b011:
out=hw3;
3'b100:
out=hw4;
3'b101:
out=hw5;
3'b110:
out=hw6;
3'b111:
out=hw7;
endcase
end
endmodule
modules_ram(wr_clk,wr_en,wr_addr,data_in,rd_clk,rd_en,rd_addr,data_out);
inputwr_clk,wr_en,rd_clk,rd_en;
input[7:
0]data_in;
input[7:
0]wr_addr,rd_addr;
output[7:
0]data_out;
reg[7:
0]data_out;
reg[7:
0]mem[255:
0];
always@(posedgewr_clk)
if(wr_en)
mem[wr_addr]<=data_in;
always@(posedgerd_clk)
if(rd_en)
data_out<=mem[rd_addr];
endmodule
modulec_ram(wr_clk,wr_en,wr_addr,data_in,rd_clk,rd_en,rd_addr,data_out);
inputwr_clk,wr_en,rd_clk,rd_en;
input[7:
0]data_in;
input[7:
0]wr_addr,rd_addr;
output[7:
0]data_out;
reg[7:
0]data_out;
reg[7:
0]mem[255:
0];
always@(posedgewr_clk)
if(wr_en)
mem[wr_addr]<=data_in;
always@(posedgerd_clk)
if(rd_en)
data_out<=mem[rd_addr];
endmodule
modulefenlu(data_in,sel,reg0,reg1,reg2,reg3,reg4,reg5,reg6,reg7);
input[7:
0]data_in;
input[2:
0]sel;
output[7:
0]reg0,reg1,reg2,reg3,reg4,reg5,reg6,reg7;
reg[7:
0]reg0,reg1,reg2,reg3,reg4,reg5,reg6,reg7;
always@(data_in)
case(sel)
3'b000:
reg0=data_in;
3'b001:
reg1=data_in;
3'b010:
reg2=data_in;
3'b011:
reg3=data_in;
3'b100:
reg4=data_in;
3'b101:
reg5=data_in;
3'b110:
reg6=data_in;
3'b111:
reg7=data_in;
endcase
endmodule
moduleyiwei(clk,rst,data_in,data_out);
inputclk,rst;
input[7:
0]data_in;
outputdata_out;
regdata;
always@(posedgeclk)
if(rst)
data=0;
else
data=data_in[7];
assigndata_in={data_in[6:
0],1'b0};
assigndata_out=data;
endmodule
modulebit(clk,rst,count_8,count_256);
inputrst,clk;
output[2:
0]count_8;
output[7:
0]count_256;
reg[2:
0]count_8;
reg[7:
0]count_256;
always@(posedgeclk)
begin
if(rst)begin
count_8<=3'b000;
count_256<=8'b0000_0000;
end
elsebegin
count_256<=count_256+1;
if(count_256%8==0)
count_8<=count_8+1;
end
end
endmodule
modulemux_s(hw0,hw1,hw2,hw3,hw4,hw5,hw6,hw7,hw8,hw9,hw10,hw11,hw12,hw13,hw14,hw15,
out0,out1,out2,out3,out4,out5,out6,out7,out8,out9,out10,out11,out12,out13,out14,out15,
sel0,sel1,sel2,sel3,sel4,sel5,sel6,sel7,sel8,sel9,sel10,sel11,sel12,sel13,sel14,sel15);
output[7:
0]out0,out1,out2,out3,out4,out5,out6,out7,out8,out9,out10,out11,out12,out13,out14,out15;
input[7:
0]hw0,hw1,hw2,hw3,hw4,hw5,hw6,hw7,hw8,hw9,hw10,hw11,hw12,hw13,hw14,hw15;
input[3:
0]sel0,sel1,sel2,sel3,sel4,sel5,sel6,sel7,sel8,sel9,sel10,sel11,sel12,sel13,sel14,sel15;
reg[7:
0]out0,out1,out2,out3,out4,out5,out6,out7,out8,out9,out10,out11,out12,out13,out14,out15;
always@(hw0orhw1orhw2orhw3orhw4orhw5orhw6orhw7orhw8orhw9orhw10
orhw11orhw12orhw13orhw14orhw15orsel0)
begin
case(sel0)
4'b0000:
out0=hw0;
4'b0001:
out0=hw1;
4'b0010:
out0=hw2;
4'b0011:
out0=hw3;
4'b0100:
out0=hw4;
4'b0101:
out0=hw5;
4'b0110:
out0=hw6;
4'b0111:
out0=hw7;
4'b1000:
out0=hw8;
4'b1001:
out0=hw9;
4'b1010:
out0=hw10;
4'b1011:
out0=hw11;
4'b1100:
out0=hw12;
4'b1101:
out0=hw13;
4'b1110:
out0=hw14;
4'b1111:
out0=hw15;
endcase
end
always@(hw0orhw1orhw2orhw3orhw4orhw5orhw6orhw7orhw8orhw9orhw10
orhw11orhw12orhw13orhw14orhw15orsel1)
begin
case(sel0)
4'b0000:
out1=hw0;
4'b0001:
out1=hw1;
4'b0010:
out1=hw2;
4'b0011:
out1=hw3;
4'b0100:
out1=hw4;
4'b0101:
out1=hw5;
4'b0110:
out1=hw6;
4'b0111:
out1=hw7;
4'b1000:
out1=hw8;
4'b1001:
out1=hw9;
4'b1010:
out1=hw10;
4'b1011:
out1=hw11;
4'b1100:
out1=hw12;
4'b1101:
out1=hw13;
4'b1110:
out1=hw14;
4'b1111:
out1=hw15;
endcase
end
always@(hw0orhw1orhw2orhw3orhw4orhw5orhw6orhw7orhw8orhw9orhw10
orhw11orhw12orhw13orhw14orhw15orsel2)
begin
case(sel0)
4'b0000:
out2=hw0;
4'b0001:
out2=hw1;
4'b0010:
out2=hw2;
4'b0011:
out2=hw3;
4'b0100:
out2=hw4;
4'b0101:
out2=hw5;
4'b0110:
out2=hw6;
4'b0111:
out2=hw7;
4'b1000:
out2=hw8;
4'b1001:
out2=hw9;
4'b1010:
out2=hw10;
4'b1011:
out2=hw11;
4'b1100:
out2=hw12;
4'b1101:
out2=hw13;
4'b1110:
out2=hw14;
4'b1111:
out2=hw15;
endcase
end
always@(hw0orhw1orhw2orhw3orhw4orhw5orhw6orhw7orhw8orhw9orhw10
orhw11orhw12orhw13orhw14orhw15orsel3)
begin
case(sel0)
4'b0000:
out3=hw0;
4'b0001:
out3=hw1;
4'b0010:
out3=hw2;
4'b0011:
out3=hw3;
4'b0100:
out3=hw4;
4'b0101:
out3=hw5;
4'b0110:
out3=hw6;
4'b0111:
out3=hw7;
4'b1000:
out3=hw8;
4'b1001:
out3=hw9;
4'b1010:
out3=hw10;
4'b1011:
out3=hw11;
4'b1100:
out3=hw12;
4'b1101:
out3=hw13;
4'b1110:
out3=hw14;
4'b1111:
out3=hw15;
endcase
end
always@(hw0orhw1orhw2orhw3orhw4orhw5orhw6orhw7orhw8orhw9orhw10
orhw11orhw12orhw13orhw14orhw15orsel4)
begin
case(sel0)
4'b0000:
out4=hw0;
4'b0001:
out4=hw1;
4'b0010:
out4=hw2;
4'b0011:
out4=hw3;
4'b0100:
out4=hw4;
4'b0101:
out4=hw5;
4'b0110:
out4=hw6;
4'b0111:
out4=hw7;
4'b1000:
out4=hw8;
4'b1001:
out4=hw9;
4'b1010:
out4=hw10;
4'b1011:
out4=hw11;
4'b1100:
out4=hw12;
4'b1101:
out4=hw13;
4'b1110:
out4=hw14;
4'b1111:
out4=hw15;
endcase
end
always@(hw0orhw1orhw2orhw3orhw4orhw5orhw6orhw7orhw8orhw9orhw10
orhw11orhw12orhw13orhw14orhw15orsel5)
begin
case(sel0)
4'b0000:
out5=hw0;
4'b0001:
out5=hw1;
4'b0010:
out5=hw2;
4'b0011:
out5=hw3;
4'b0100:
out5=hw4;
4'b0101:
out5=hw5;
4'b0110:
out5=hw6;
4'b0111:
out5=hw7;
4'b1000:
out5=hw8;
4'b1001:
out5=hw9;
4'b1010:
out5=hw10;
4'b1011:
out5=hw11;
4'b1100:
out5=hw12;
4'b1101:
out5=hw13;
4'b1110:
out5=hw14;
4'b1111:
out5=hw15;
endcase
end
always@(hw0orhw1orhw2orhw3orhw4orhw5orhw6orhw7orhw8orhw9orhw10
orhw11orhw12orhw13orhw14orhw15orsel6)
begin
case(sel0)
4'b0000:
out6=hw0;
4'b0001:
out6=hw1;
4'b0010:
out6=hw2;
4'b0011:
out6=hw3;
4'b0100:
out6=hw4;
4'b0101:
out6=hw5;
4'b0110:
out6=hw6;
4'b0111:
out6=hw7;
4'b1000:
out6=hw8;
4'b1001:
out6=hw9;
4'b1010:
out6=hw10;
4'b1011:
out6=hw11;
4'b1100:
out6=hw12;
4'b1101:
out6=hw13;
4'b1110:
out6=hw14;
4'b1111:
out6=hw15;
endcase
end
always@(hw0orhw1orhw2orhw3orhw4orhw5orhw6orhw7orhw8orhw9orhw10
orhw11orhw12orhw13orhw14orhw15orsel7)
begin
case(sel0)
4'b0000:
out7=hw0;
4'b0001:
out7=hw1;
4'b0010:
out7=hw2;
4'b0011:
out7=hw3;
4'b0100:
out7=hw4;
4'b0101:
out7=hw5;
4'b0110:
out7=hw6;
4'b0111:
out7=hw7;
4'b1000:
out7=hw8;
4'b1001:
out7=hw9;
4'b1010:
out7=hw10;
4'b1011:
out7=hw11;
4'b1100:
out7=hw12;
4'b1101:
out7=hw13;
4'b1110:
out7=hw14;
4'b1111:
out7=hw15;
endcase
end
always@(hw0orhw1orhw2orhw3orhw4orhw5orhw6orhw7orhw8orhw9orhw10
orhw11orhw12orhw13orhw14orhw15orsel8)
begin
case(sel0)
4'b0000:
out8=hw0;
4'b0001:
out8=hw1;
4'b0010:
out8=hw2;
4'b0011:
out8=hw3;
4'b0100:
out8=hw4;
4'b0101:
out8=hw5;
4'b0110:
out8=hw6;
4'b0111:
out8=hw7;
4'b1000:
out8=hw8;
4'b1001:
out8=hw9;
4'b1010:
out8=hw10;
4'b1011:
out8=hw11;
4'b1100:
out8=hw12;
4'b1101:
out8=hw13;
4'b1110:
out8=hw14;
4'b1111:
out8=hw15;
endcase
end
always@(hw0orhw1orhw2orhw3orhw4orhw5orhw6orhw7orhw8orhw9orhw10
orhw11orhw12orhw13orhw14orhw15orsel9)
begin
case(sel0)
4'b0000:
out9=hw0;
4'b0001:
out9=hw1;
4'b0010:
out9=hw2;
4'b0011:
out9=hw3;
4'b0100:
out9=hw4;
4'b0101:
out9=hw5;
4'b0110:
out9=hw6;
4'b0111:
out9=hw7;
4'b1000:
out9=hw8;
4'b1001:
out9=hw9;
4'b1010:
out9=hw10;
4'b1011:
out9=hw11;
4'b1100:
out9=hw12;
4'b1101:
out9=hw13;
4'b1110:
out9=hw14;
4'b1111:
out9=hw15;
endcase
end
always@(hw0orhw1orhw2orhw3orhw4orhw5orhw6orhw7orhw8orhw9orhw10
orhw11orhw12orhw13orhw14orhw15orsel10)
begin
case(sel0)
4'b0000:
out10=hw0;
4'b0001:
out10=hw1;
4'b0010:
out10=hw2;
4'b0011:
out10=hw3;
4'b0100:
out10=hw4;
4'b0101:
out10=hw5;
4'b0110:
out10=hw6;
4'b0111:
out10=hw7;
4'b1000:
out10=hw8;
4'b1001:
out10=hw9;
4'b1010:
out10=hw10;
4'b1011:
out10=hw11;
4'b1100:
out10=hw12;
4'b1101:
out10=hw13;
4'b1110:
out10=hw14;
4'b1111:
out10=hw15;
endcase
end
always@(hw0orhw1orhw2orhw3orhw4orhw5orhw6orhw7orhw8orhw9orhw10
orhw11orhw12orhw13orhw14orhw15orsel11)
begin
case(sel0)
4'b0000:
out11=hw0;
4'b0001:
out11=hw1;
4'b0010:
out11=hw2;
4'b0011:
out11=hw3;
4'b0100:
out11=hw4;
4'b0101:
out11=hw5;
4'b0110:
out11=hw6;
4'b0111:
out11=hw7;
4'b1000:
out11=hw8;
4'b1001:
out11=hw9;
4'b1010:
out11=hw10;
4'b1011:
out11=hw11;
4'b1100:
out11=hw12;
4'b1101:
out11=hw13;
4'b1110:
out11=hw14;
4'b1111:
out11=hw15;
endcase
end
always@(hw0orhw1orhw2orhw3orhw4orhw5orhw6orhw7orhw8orhw9orhw10
orhw11orhw12orhw13orhw14orhw15orsel12)
begin
case(sel0)
4'b0000:
out12=hw0;
4'b0001:
out12=hw1;
4'b0010:
out12=hw2;
4'b0011:
out12=hw3;
4'b0100:
out12=hw4;
4'b0101:
out12=hw5;
4'b0110:
out12=hw6;
4'b0111:
out12=hw7;
4'b10