EDA电子钟设计.docx
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EDA电子钟设计
电子设计自动化EDA课程设计
题目电子钟设计
专业
班级
学号
姓名
一、基本功能要求：
基本功能：
设计一个电子时钟，要求可以显示时、分、秒，用户可以设置时间。
扩展功能：
秒表功能，闹钟功能，调整数码管的亮度
二、工作原理：
编写分频语句，用来产生合适的驱动频率，分别编写时钟各位语句，通过例化语句连接，再写一个闹钟设置语句（各自独立），通过闹钟与时钟的比较（比较器）来控制是否发声，再编写跑表语句，可通过三选一选择器进入。
三、操作说明：
模式一：
调节时钟时。
键1用来对分位加1，键4选择时钟位。
模式二：
由模式一按一下键7进入秒表功能，键4开始，再按暂停，键1复位。
模式三：
由模式二按一下键7进入闹钟时间设置，键1用来对分位加1，键4选择时钟位。
模式四：
由模式散按一下键7进入亮度调节功能，键4调节亮度，三个亮度模式可选。
再按键7从新回到显示模块。
四、引脚设置：
五、RTL图：
六、VHDL源码
libraryieee;--主程序
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entityclockis
port（clk_10M:
instd_logic;
jian1,jian4,jian7,jian8:
instd_logic;
sg:
outstd_logic_vector（6downto0）;---数码管段显示
bt:
outstd_logic_vector（7downto0）;---数码管位显示
speaker:
outstd_logic）;
endentity;
architecturebavofclockis
componentfenpin--分频
port（
clk_10M:
instd_logic;
clk_10000:
outstd_logic;
clk_100:
outstd_logic;
clk_1:
outstd_logic
）;
endcomponent;
componentpaobiao--跑表
port（clk_1:
instd_logic;
jian8:
instd_logic;
shishi1,shige1,fenshi1,fenge1,miaoshi1,miaoge1:
inintegerrange0to9;
shishi2,shige2,fenshi2,fenge2,miaoshi2,miaoge2:
outintegerrange0to9）;
endcomponent;
componentxianshi--扫描显示
port（clk_10000:
instd_logic;
jian4:
instd_logic;
moshi:
inintegerrange0to4;
a0,a1,a3,a4,a6,a7:
inintegerrange0to9;
sg11:
outstd_logic_vector（6downto0）;
bt11:
outstd_logic_vector（7downto0））;
endcomponent;
componentmoshi--模式转换
port（jian7:
instd_logic;
moshi:
outintegerrange0to4）;
endcomponent;
componentmux5_1--五选一选择器
port（moshi:
inintegerrange0to4;
shishi1,shige1,fenshi1,fenge1,miaoshi1,miaoge1:
inintegerrange0to9;
shishi2,shige2,fenshi2,fenge2,miaoshi2,miaoge2:
inintegerrange0to9;
shishi3,shige3,fenshi3,fenge3,miaoshi3,miaoge3:
inintegerrange0to9;
fenshi,fenge,miaoshi,miaoge,xmiaoshi,xmiaoge:
inintegerrange0to9;
a0,a1,a3,a4,a6,a7:
outintegerrange0to9）;
endcomponent;
componentsettime--设置当前时间
port（moshi:
inintegerrange0to4;
jian4,jian1:
instd_logic;
shishi,shige,fenshi,fenge,miaoshi,miaoge:
outintegerrange0to9）;
endcomponent;
componentmiaobiaois--秒表
port（clk_100:
instd_logic;
moshi:
inintegerrange0to4;
jian1,jian4:
instd_logic;
fenshi,fenge,miaoshi,miaoge,xmiaoshi,xmiaoge:
outintegerrange0to9）;
endcomponent;
componentnaozhongsetis--闹钟时间设置
port（moshi:
inintegerrange0to4;
jian4,jian1:
instd_logic;
shishi,shige,fenshi,fenge,miaoshi,miaoge:
outintegerrange0to9）;
endcomponent;
componentnaozhongspeakeris--闹钟喇叭输出
port（clk_100:
instd_logic;
shishi1,shige1,fenshi1,fenge1,miaoshi1,miaoge1:
inintegerrange0to9;
shishi2,shige2,fenshi2,fenge2,miaoshi2,miaoge2:
inintegerrange0to9;
speaker:
outstd_logic）;
endcomponent;
signalmoshis:
integerrange0to4;--信号声明
signalshishi1s,shige1s,fenshi1s,fenge1s,miaoshi1s,miaoge1s:
integerrange0to9;
signalshishi2s,shige2s,fenshi2s,fenge2s,miaoshi2s,miaoge2s:
integerrange0to9;
signalshishi3s,shige3s,fenshi3s,fenge3s,miaoshi3s,miaoge3s:
integerrange0to9;
signalfenshis,fenges,miaoshis,miaoges,xmiaoshis,xmiaoges:
integerrange0to9;
signala0s,a1s,a3s,a4s,a6s,a7s:
integerrange0to9;
signalclk_10000s,clk_100s,clk_1s:
std_logic;
begin--元件例化
u1:
paobiaoportmap（clk_1=>clk_1s,
jian8=>jian8,
shishi1=>shishi2s,shige1=>shige2s,fenshi1=>fenshi2s,fenge1=>fenge2s,miaoshi1=>miaoshi2s,miaoge1=>miaoge2s,
shishi2=>shishi1s,shige2=>shige1s,fenshi2=>fenshi1s,fenge2=>fenge1s,miaoshi2=>miaoshi1s,miaoge2=>miaoge1s）;
u2:
xianshiportmap（clk_10000=>clk_10000s,
jian4=>jian4,
moshi=>moshis,
a0=>a0s,a1=>a1s,a3=>a3s,a4=>a4s,a6=>a6s,a7=>a7s,
sg11=>sg,bt11=>bt）;
u3:
setting
portmap（moshi=>moshis,jian1=>jian1,jian4=>jian4,shishi=>shishi2s,shige=>shige2s,fenshi=>fenshi2s,fenge=>fenge2s,miaoshi=>miaoshi2s,miaoge=>miaoge2s）;
u4:
moshiportmap（jian7=>jian7,
moshi=>moshis）;
u5:
mux5_1portmap（moshi=>moshis,
shishi1=>shishi1s,shige1=>shige1s,fenshi1=>fenshi1s,fenge1=>fenge1s,miaoshi1=>miaoshi1s,miaoge1=>miaoge1s,
shishi2=>shishi2s,shige2=>shige2s,fenshi2=>fenshi2s,fenge2=>fenge2s,miaoshi2=>miaoshi2s,miaoge2=>miaoge2s,
shishi3=>shishi3s,shige3=>shige3s,fenshi3=>fenshi3s,fenge3=>fenge3s,miaoshi3=>miaoshi3s,miaoge3=>miaoge3s,
fenshi=>fenshis,fenge=>fenges,miaoshi=>miaoshis,miaoge=>miaoges,xmiaoshi=>xmiaoshis,xmiaoge=>xmiaoges,
a0=>a0s,a1=>a1s,a3=>a3s,a4=>a4s,a6=>a6s,a7=>a7s）;
u6:
miaobiaoportmap（clk_100=>clk_100s,moshi=>moshis,
jian1=>jian1,jian4=>jian4,
fenshi=>fenshis,fenge=>fenges,miaoshi=>miaoshis,miaoge=>miaoges,xmiaoshi=>xmiaoshis,xmiaoge=>xmiaoges）;
u7:
fenpinportmap（clk_10M=>clk_10m,
clk_10000=>clk_10000s,
clk_100=>clk_100s,
clk_1=>clk_1s）;
u8:
naozhongsetportmap（moshi=>moshis,
jian1=>jian1,jian4=>jian4,
shishi=>shishi3s,shige=>shige3s,fenshi=>fenshi3s,fenge=>fenge3s,miaoshi=>miaoshi3s,miaoge=>miaoge3s）;
u9:
naozhongspeakerportmap（clk_100=>clk_100s,speaker=>speaker,
shishi1=>shishi3s,shige1=>shige3s,fenshi1=>fenshi3s,fenge1=>fenge3s,miaoshi1=>miaoshi3s,miaoge1=>miaoge3s,
shishi2=>shishi1s,shige2=>shige1s,fenshi2=>fenshi1s,fenge2=>fenge1s,miaoshi2=>miaoshi1s,miaoge2=>miaoge1s）;
end;
libraryieee;--五选一选择器
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entitymux5_1is
port（moshi:
inintegerrange0to4;
shishi1,shige1,fenshi1,fenge1,miaoshi1,miaoge1:
inintegerrange0to9;
shishi2,shige2,fenshi2,fenge2,miaoshi2,miaoge2:
inintegerrange0to9;
shishi3,shige3,fenshi3,fenge3,miaoshi3,miaoge3:
inintegerrange0to9;
fenshi,fenge,miaoshi,miaoge,xmiaoshi,xmiaoge:
inintegerrange0to9;
a0,a1,a3,a4,a6,a7:
outintegerrange0to9）;
endentitymux5_1;
architecturebhvofmux5_1is
begin
process（shishi1,shige1,fenshi1,fenge1,miaoshi1,miaoge1,
shishi2,shige2,fenshi2,fenge2,miaoshi2,miaoge2,
shishi3,shige3,fenshi3,fenge3,miaoshi3,miaoge3,
fenshi,fenge,miaoshi,miaoge,xmiaoshi,xmiaoge,
moshi）
begin
casemoshiis
when0=>a0<=shishi1;a1<=shige1;a3<=fenshi1;a4<=fenge1;a6<=miaoshi1;a7<=miaoge1;
when1=>a0<=shishi2;a1<=shige2;a3<=fenshi2;a4<=fenge2;a6<=miaoshi2;a7<=miaoge2;
when2=>a0<=fenshi;a1<=fenge;a3<=miaoshi;a4<=miaoge;a6<=xmiaoshi;a7<=xmiaoge;
when3=>a0<=shishi3;a1<=shige3;a3<=fenshi3;a4<=fenge3;a6<=miaoshi3;a7<=miaoge3;
when4=>a0<=8;a1<=8;a3<=8;a4<=8;a6<=8;a7<=8;
endcase;
endprocess;
end;
libraryieee;--模式转换
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entitymoshiis
port（jian7:
instd_logic;--按键7选择模式
moshi:
outintegerrange0to4）;--共计5个模式
end;
architectureoneofmoshiis
signalmoshis:
integerrange0to4;
begin
process（jian7）
begin
ifjian7'eventandjian7='1'then
ifmoshis=4then
moshis<=0;
elsemoshis<=moshis+1;
endif;
endif;
endprocess;
moshi<=moshis;
end;
libraryieee;--秒表
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entitymiaobiaois
port（clk_100:
instd_logic;
moshi:
inintegerrange0to4;
jian1,jian4:
instd_logic;
fenshi,fenge,miaoshi,miaoge,xmiaoshi,xmiaoge:
outintegerrange0to9）;
endentity;
architecturebhvofmiaobiaois
signalfen,miao,xmiao:
integerrange0to99;
signalstart:
std_logic:
='0';
signalreset:
std_logic:
='0';
begin
process（clk_100,jian1,jian4,moshi,reset,start）
begin
ifmoshi=2then
ifreset='1'then
fen<=0;
miao<=0;
xmiao<=0;
elsifstart='1'then
elsifclk_100'eventandclk_100='1'then
ifxmiao=99then
xmiao<=0;
miao<=miao+1;
elsifmiao>59then
miao<=0;
fen<=fen+1;
elsiffen>23then
fen<=0;
elsexmiao<=xmiao+1;
endif;
endif;
endif;
endprocess;
process（jian4,start）
begin
ifjian4'eventandjian4='1'then
start<=notstart;
elsestart<=start;
endif;
endprocess;
process（jian1,reset）
begin
ifjian1'eventandjian1='1'then
reset<=notreset;
elsereset<=reset;
endif;
endprocess;
xmiaoge<=xmiaorem10;
xmiaoshi<=xmiao/10;
miaoge<=miaorem10;
miaoshi<=miao/10;
fenge<=fenrem10;
fenshi<=fen/10;
end;
libraryieee;--设置当前时间
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entitysettimeis
port（moshi:
inintegerrange0to4;
jian4,jian1:
instd_logic;
shishi,shige,fenshi,fenge,miaoshi,miaoge:
outintegerrange0to9）;
endentity;
architecturebavofsettimeis
signala:
integerrange0to5;--数码管显示时间部分位选择信号
signalshishi1,shige1,fenshi1,fenge1,miaoshi1,miaoge1:
integerrange0to9;
begin
process（moshi,jian4）
begin
ifmoshi=1then
ifjian4'eventandjian4='1'then
ifa<5then
a<=a+1;
elsea<=0;
endif;
endif;
endif;
endprocess;
process（moshi,a,jian1）
begin
ifmoshi=1then
ifa=0then
ifjian1'eventandjian1='1'then
ifmiaoge1=9then
miaoge1<=0;
elsemiaoge1<=miaoge1+1;
endif;
endif;
endif;
ifa=1then
ifjian1'eventandjian1='1'then
ifmiaoshi1=5then
miaoshi1<=0;
elsemiaoshi1<=miaoshi1+1;
endif;
endif;
endif;
ifa=2then
ifjian1'eventandjian1='1'then
iffenge1=9then
fenge1<=0;
elsefenge1<=fenge1+1;
endif;
endif;
endif;
ifa=3then
ifjian1'eventandjian1='1'then
iffenshi1=5then
fenshi1<=0;
elsefenshi1<=fenshi1+1;
endif;
endif;
endif;
ifa=4then
ifjian1'eventandjian1='1'then
ifshige1=9then
shige1<=0;
elseshige1<=shige1+1;
endif;
endif;
endif;
ifa=5then
ifjian1'eventandjian1='1'then
ifshishi1=2then
shishi1<=0;
elseshishi1<=shishi1+1;
endif;
endif;
endif;
endif;
endprocess;
miaoge<=miaoge1;
miaoshi<=miaoshi1;
fenge<=fenge1;
fenshi<=fenshi1;
shige<=shige1;
shishi<=shishi1;
end;
libraryieee;--分频
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entityfenpin
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