实验报告模板Word格式.docx
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//0110
0]d_nor=~（a|b）;
//0111
0]d_lui={b[15:
0],16'
h0};
//100x
0]d_slt=a<
b?
1:
0;
0]d_sltu=（a[31]&
&
~b[31]）||（a[31]&
b[31]&
a>
b）||（~a[31]&
~b[31]&
a<
b）;
0]d_and_or=aluc[0]?
d_or:
d_and;
0]d_xor_nor=aluc[0]?
d_nor:
d_xor;
0]d_and_or_xor_nor=aluc[1]?
d_xor_nor:
d_and_or;
0]d_slt_sltu=aluc[0]?
d_slt:
d_sltu;
0]d_lui_slt_sltu=aluc[1]?
d_slt_sltu:
d_lui;
0]d_as;
0]d_sh;
wirecarry_as;
wirenegative_as;
wireoverflow_as;
wirecarry_sh;
addsub32as32（a,b,aluc[0],aluc[1],d_as,carry_as,overflow_as）;
shiftshifter（b,a[4:
0],~aluc[1],~aluc[0],d_sh,carry_sh）;
mux4x32select_d（d_as,d_and_or_xor_nor,d_lui_slt_sltu,d_sh,aluc[3:
2],r）;
mux4x1select_carry（carry_as,1'
b0,1'
b0,carry_sh,aluc[3:
2],carry）;
mux4x1select_overflow（overflow_as,1'
b0,overflow_sh,aluc[3:
2],overflow）;
assignzero=~|r;
assignnegative=r[31];
endmodule
2.regfile
moduleregfile（
input[4:
0]raddr1,
0]raddr2,
0]wdata,
0]waddr,
inputwe,
inputclk,
inputrst,
0]radata1,
0]radata2
reg[31:
0]register[0:
31];
assignradata1=（raddr1==0）?
0:
register[raddr1];
assignradata2=（raddr2==0）?
register[raddr2];
integeri;
always@（posedgerstornegedgeclk）begin
if（rst==1）
begin
for（i=1;
i<
32;
i=i+1）begin
register[i]<
=0;
end
end
elsebegin
register[0]<
=32'
b0;
if（（waddr!
=0）&
we）begin
register[waddr]<
=wdata;
end
end
3.CP0
moduleCoprocessor0（
input[4:
0]C0adr,
input[31:
0]C0Wdata,
inputC0Write,
0]InteCause,
inputInterrupt,
outputInteAccept,
output[31:
0]C0State,
outputreg[31:
0]C0Data
parameterEPCadr=5'
h0;
parameterCauseadr=5'
h1;
parameterStateadr=5'
h2;
reg[31:
0]EPC;
0]Cause;
0]State;
initialbegin
State<
=32'
Cause<
EPC<
end
assignC0State=State;
assignInteAccept=
（C0Write&
（C0adr==Stateadr））&
Interrupt&
~C0Wdata[1]||
~（C0Write&
~（C0Write&
（C0adr==Causeadr））&
~State[1];
always@（posedgeclk）begin
if（C0Write）begin
if（C0adr==EPCadr）begin
EPC<
=C0Wdata;
if（Interrupt&
~State[1]）begin
State<
=State|32'
b10;
Cause<
=InteCause;
if（C0adr==Stateadr）begin
~C0Wdata[1]）begin
State<
=C0Wdata|32'
Cause<
elsebegin
if（C0adr==Causeadr）begin
Cause<
elsebegin
if（Interrupt&
State<
case（C0adr）
EPCadr:
begin
C0Data<
=EPC;
Causeadr:
=Cause;
Stateadr:
=State;
endcase
4.pc_reg
modulepc_reg（
inputclk,
inputrst,
0]data_in,
outputreg[31:
0]data_out
always@（posedgeclk）begin
if（rst==1）begin
data_out<
elsebegin
data_out<
=data_in;
5.mul
modulemul（
inputu,//1有符号，0无符号
0]hi,
0]lo
reg[32:
0]a_bi[32:
0];
integerj;
wire[32:
0]ai;
0]bi;
wire[65:
0]z;
assignai=u?
{a[31],a}:
{1'
b0,a};
assignbi=u?
{b[31],b}:
b0,b};
always@（*）begin
if（we）
for（i=0;
i=i+1）
for（j=0;
j<
j=j+1）
a_bi[i][j]=ai[i]&
bi[j];
a_bi[i][32]=~（ai[i]&
bi[32]）;
for（j=0;
a_bi[32][j]=~（ai[32]&
bi[j]）;
a_bi[32][32]=ai[32]&
bi[32];
assignz={33'
b1,a_bi[0][32],a_bi[0][31:
0]}+
（（（（{32'
b0,a_bi[1][32],a_bi[1][31:
0],1'
b0}+
{31'
b0,a_bi[2][32],a_bi[2][31:
0],2'
b0}）+
（{30'
b0,a_bi[3][32],a_bi[3][31:
0],3'
{29'
b0,a_bi[4][32],a_bi[4][31:
0],4'
b0}））+
（（{28'
b0,a_bi[5][32],a_bi[5][31:
0],5'
{27'
b0,a_bi[6][32],a_bi[6][31:
0],6'
（{26'
b0,a_bi[7][32],a_bi[7][31:
0],7'
{25'
b0,a_bi[8][32],a_bi[8][31:
0],8'
b0}）））+
（（（{24'
b0,a_bi[9][32],a_bi[9][31:
0],9'
{23'
b0,a_bi[10][32],a_bi[10][31:
0],10'
（{22'
b0,a_bi[11][32],a_bi[11][31:
0],11'
{21'
b0,a_bi[12][32],a_bi[12][31:
0],12'
（（{20'
b0,a_bi[13][32],a_bi[13][31:
0],13'
{19'
b0,a_bi[14][32],a_bi[14][31:
0],14'
（{18'
b0,a_bi[15][32],a_bi[15][31:
0],15'
{17'
b0,a_bi[16][32],a_bi[16][31:
b0}））））+
（（（（{16'
b0,a_bi[17][32],a_bi[17][31:
0],17'
{15'
b0,a_bi[18][32],a_bi[18][31:
0],18'
（{14'
b0,a_bi[19][32],a_bi[19][31:
0],19'
{13'
b0,a_bi[20][32],a_bi[20][31:
0],20'
（（{12'
b0,a_bi[21][32],a_bi[21][31:
0],21'
{11'
b0,a_bi[22][32],a_bi[22][31:
0],22'
（{10'
b0,a_bi[23][32],a_bi[23][31:
0],23'
{9'
b0,a_bi[24][32],a_bi[24][31:
0],24'
（（（{8'
b0,a_bi[25][32],a_bi[25][31:
0],25'
{7'
b0,a_bi[26][32],a_bi[26][31:
0],26'
（{6'
b0,a_bi[27][32],a_bi[27][31:
0],27'
{5'
b0,a_bi[28][32],a_bi[28][31:
0],28'
（（{4'
b0,a_bi[29][32],a_bi[29][31:
0],29'
{3'
b0,a_bi[30][32],a_bi[30][31:
0],30'
（{2'
b0,a_bi[31][32],a_bi[31][31:
0],31'
{1'
b1,a_bi[32][32],a_bi[32][31:
0],32'
b0}））））;
assignhi=z[63:
32];
assignlo=z[31:
6.div
modulediv（
0]a1,//被除数低位
0]a2,//被除数高位
0]b,//除数
inputen,//使能
inputu,//0无符号，1有符号
0]q,//商
0]r//余数
reg[5:
0]count;
//32
reg[66:
0]a;
count=0;
integeri;
always@（*）begin
if（en==1）begin
if（u==0）begin
a={2'
b00,a2[31:
0],a1[31:
b0};
a=a-{b[31:
0],33'
b000000000000000000000000000000000};
for（i=0;
i=i+1）begin
if（a[66]+a[65]==2）begin
a[0]=0;
a=a<
<
1;
a=a+{b[31:
end
elsebegin
a[0]=1;
a=a-{b[31:
end
if（a[66]+a[65]==2）begin
q={a[31:
0]};
r={a[64:
33]};
if（a2[31]==b[31]）begin
a={2'
if（a[63]!
=b[31]）begin
if（a[64]==1）begin
7.bz0//自己设计模块针对bgez、bgtz、blez、bltz四条指令
modulebz（
input[1:
outputregz
case（b）
2'
b00:
//>
=0
if（a[31]==0）
z<
=1;
else
=0;
b01:
//<
if（a[31]==1）
b10:
if（a[31]==1||a==0）
b11:
if（a[31]==0||a!
=0）
endcase
8.imem
moduleinstmem（
0]pc,
0]inst
0]a[0:
255];
initialbegin
$readmemh（"
1.txt"
a）;
assigninst=a[pc[31:
2]];
9.dmem//因lh、lb、sh、sb等指令对dmem做了改动
moduleram（
inputram_ena,
0]c,//0xlw/sw,10lh/sh,11lb/hb
inputu,
0]addr,
0]data_out
）;
reg[7:
20470];
always@（posedgeclk）begin
if（ram_ena）
case（c）
2'
begin
a[{addr[31:
2],2'
b00}]<
=data_in[7:
b00}+1]<
=data_in[15:
8];
b00}+2]<
=data_in[23:
16];
b00}+3]<
=data_in[31:
24];
1],1'
b0}]<
b0}+1]<
a[addr]<
default:
endcase
end
data_out<
={a[{addr[31:
b00}+3],a[{addr[31:
b00}+2],a[{addr[31:
b00}+1],a[{addr[31:
b00}]};
={{16{u&
a[{addr[31:
b0}+1][7]}},a[{addr[31:
b0}+1],a[{addr[31:
b0}]};
={{24{u&
a[addr][7]}},a[addr]};
四、应用程序
八数码
addi$10,$0,1
addi$11,$0,2
addi$12,$0,3
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