多功能数字时钟VHDL源代码Word文档格式.docx
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0011"
0111"
then---当分的低位为1或3或5或7时
q500<
='
;
----低频输出为1
else
0'
----否则输出为0
endif;
ands0="
then---当秒高位为5，低位为9时且分高位为5，----分低位为9时，也就是“59分59秒”的时候“报时”
qlk<
-----高频输出为1
endprocess;
process（h1,h0,m1,m0,nao_h_h,nao_h_l,nao_m_h,nao_m_l）
ifdip（0）='
andh1=nao_h_handh0=nao_h_landm1=nao_m_handm0=nao_m_lthen
q1khz<
endbehav;
braz模块：
useieee.std_logic_unsigned.all;
useieee.std_logic_arith.all;
entitybrazis
port（dip:
f1khz,f500hz:
braz:
endentity;
architecturebehaveofbrazis
begin
process（q500,qlk,dip）
ifdip="
0010"
ordip="
1110"
1010"
0110"
thenbraz<
ifq500='
=f500hz;
elsifqlk='
orq1khz='
=f1khz;
elsebraz<
endbehave;
秒计数模块：
entitycount60is
port（carry:
one:
outstd_logic_vector（3downto0）;
ten:
full:
outstd_logic）;
endcount60;
architecturebehaveofcount60is
begin
process（carry）
variableones:
std_logic_vector（3downto0）:
="
0000"
variabletens:
ifrising_edge（carry）then
ones:
=ones+1;
if（tens="
andones="
）thenones:
=（others=>
'
）;
tens:
full<
elsif（ones="
）thentens:
=tens+1;
ones:
one<
=ones;
ten<
=tens;
endprocess;
endbehave;
显示模块：
entitydisplayis
port（clk:
a,b,c,d:
mux_out:
wei1,wei2,wei3,wei4:
enddisplay;
architecturebehaveofdisplayis
signalsel:
integerrange0to3;
process（a,b,c,d,clk）
ifrising_edge（clk）then
sel<
=sel+1;
caseselis
when0=>
mux_out<
=a;
wei4<
wei3<
wei2<
wei1<
when1=>
=b;
when2=>
=c;
when3=>
=d;
whenothers=>
1100"
endcase;
消抖模块：
entitydebounceis
port（key:
key_valid:
enddebounce;
architecturebehaveofdebounceis
process（clk,key）
variablecnt:
integerrange0to31;
if（key="
orkey="
1011"
1101"
）then
if（clk'
）then
ifcnt=31then
key_valid<
--keypressed
--nokeypressed
cnt:
=cnt+1;
--cntplusone
=0;
--nokeypressed,theconterreset
闹钟模块：
entitynaozhongis
port（
key:
nao_h_ten:
nao_h_one:
nao_m_ten:
nao_m_one:
outstd_logic_vector（3downto0））;
endnaozhong;
architecturebehaveofnaozhongis
signalnao_h:
integerrange0to23:
=12;
signalnao_m:
integerrange0to59;
process（key,key_valid）
ifrising_edge（key_valid）then
）then
if（nao_h>
=23）thennao_h<
elsenao_h<
=nao_h+1;
if（nao_m>
=59）thennao_m<
elsenao_m<
=nao_m+1;
process（nao_h）
casenao_his
when0|10|20=>
nao_h_one<
when1|11|21=>
when2|12|22=>
when3|13|23=>
when4|14=>
0100"
when5|15=>
when6|16=>
when7|17=>
when8|18=>
1000"
when9|19=>
nao_h_one<
casenao_his
when0|1|2|3|4|5|6|7|8|9=>
nao_h_ten<
when10|11|12|13|14|15|16|17|18|19=>
when20|21|22|23=>
nao_h_ten<
process（nao_m）
casenao_mis
when0|10|20|30|40|50=>
nao_m_one<
when1|11|21|31|41|51=>
when2|12|22|32|42|52=>
when3|13|23|33|43|53=>
when4|14|24|34|44|54=>
when5|15|25|35|45|55=>
when6|16|26|36|46|56=>
when7|17|27|37|47|57=>
when8|18|28|38|48|58=>
when9|19|29|39|49|59=>
nao_m_one<
casenao_mis
nao_m_ten<
when20|21|22|23|24|25|26|27|28|29=>
when30|31|32|33|34|35|36|37|38|39=>
when40|41|42|43|44|45|46|47|48|49=>
when50|51|52|53|54|55|56|57|58|59=>
nao_m_ten<
译码输出模块：
entityyimais
port（clk:
bcd:
eight:
outstd_logic_vector（7downto0））;
endyima;
architecturebehaveofyimais
process（clk）
casebcdis
when"
=>
eight<
11000000"
11111001"
10100100"
10110000"
10011001"
10010010"
10000010"
11111000"
10000000"
10010000"
whenothers=>
11111111"
分频模块：
useieee.std_logic_unsigned;
entityfenpinis
f1khz:
endfenpin;
architecturebehavoffenpinis
signalmid:
std_logic;
variablecnum:
integerrange0to25000;
if（clk'
cnum:
=cnum+1;
ifcnum=25000then
mid<
=notmid;
cnum:
f1khz<
=mid;
1000分频模块：
entitydiv1000is
port（clk:
f1hz:
architecturebehavofdiv1000is
signalcount:
integerrange0to1000;
count<
=count+1;
ifcount=1000thenf1hz<
elsef1hz<
endif;
分计数模块：
entitymincountis
ten:
one:
endmincount;
architecturebehaveofmincountis
signalmin:
signalmin_temp:
signalmin_temp1:
process（carry）
ifrising_edge（carry）then
min_temp<
=min_temp+1;
if（min_temp=59）then
full<
min_temp<
min_temp1<
=min_temp1+1;
if（min_temp1>
=59）thenmin_temp1<
process（min）
min<
=（min_temp+min_temp1）mod（60）;
caseminis
one<
caseminis
ten<
小时计数模块：
entit
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