数字钟实验代码Word格式文档下载.docx
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//如果十位大于二,或各位大于九,或达到二十三则清零重新计数。
elseif((cnth==2)&
(cntl<
3))
begin
cnth<
=cnth;
cntl<
=cntl+1'
b1;
//十位等于二并且各位小于三时,则各位计数加一
end
elseif(cntl==9)
=cnth+1'
=4'
b0000;
//另外,十位小于二,各位计数为九时,各位清零,十位进一位
else
cntl<
//其他的情况则各位计数
end
endmodule
modulecounter10
outputreg[3:
0]q
if(~ncr)
q<
elseif(~en)
=q;
//如果en为低电位则保持
elseif(q==4'
b1001)
=q+1'
end
modulecounter6
outputreg[3:
always@(posedgecpornegedgencr)
b0101)
else
moduletop_clock
inputwireadj_min,
inputwireadj_hour,
outputwire[7:
0]hour,
0]minute,
0]second
supply1vcc;
wireminl_en;
wireminh_en;
wirehour_en;
counter10u1
.q(second[3:
0]),
.ncr(ncr),
.en(en),
.cp(cp)
counter6u2
.q(second[7:
4]),
.en(second[3:
0]==4'
h9),
//秒的个位调用十进位,十位用六进制
assignminl_en=adj_min?
(second==8'
h59):
vcc;
assignminh_en=(~adj_min&
(minute[3:
h9))||(minute[3:
h9)
&
h59);
counter10u3
.q(minute[3:
.en(minl_en),
counter6u4
.q(minute[7:
.en(minh_en),
//分的个位用十进制,十位用六进制
assignhour_en=adj_hour?
((minute==8'
h59)&
h59)):
counter24u5
.cnth(hour[7:
.cntl(hour[3:
.en(hour_en),
modulefreq
inputwireclk50M,
inputwirerst,
outputregclk1Hz
parameterCNT_1HZ=50000000;
reg[31:
0]cnt;
always@(posedgeclk50Morposedgerst)
if(rst)
clk1Hz<
=0;
cnt<
if(cnt>
=CNT_1HZ-1)
begin
cnt<
end
else
=cnt+1;
if(cnt<
CNT_1HZ/2)
clk1Hz<
//前一半计数为低电位
elseif(cnt<
CNT_1HZ-1)
=1;
//后一半计数为高电位
moduledisp
inputwireclk50M,
inputwire[3:
0]HexCode,
outputwire[7:
0]SegmentCode
reg[7:
0]Segment;
assignSegmentCode[7:
0]=~Segment[7:
0];
always@(posedgeclk50M)
case(HexCode)
4'
h0:
begin
Segment<
=8'
h3F;
end
h1:
h06;
h2:
h5B;
h3:
h4F;
h4:
h66;
h5:
h6D;
h6:
h7D;
h7:
h07;
h8:
h7F;
h9:
h6F;
end
default:
endcase
moduleradio
inputwire[7:
0]minute,
0]second,
outputregalarm_radio
always@(minuteorsecond)
if(minute==8'
h59)
case(second)
8'
h51,
h53,
h55,
h57,
h59:
alarm_radio=1'
default:
b0;
endcase//在51、53、55、57、59秒时LED灯各亮一次
elsealarm_radio=1'
modulebell
inputwirecp,
inputwiresethrkey,
inputwiresetminkey,
inputwirectrlbell,
0]hour,
0]second,
outputwirealarm_clock,
outputwire[7:
0]set_hr,set_min
supply1vdd;
wirehrh_equ;
wirehrl_equ;
wireminh_equ;
wireminl_equ;
wiretime_equ;
counter10su1
.q(set_min[3:
.ncr(vdd),
.en(setminkey),
counter6su2
.q(set_min[7:
.en(set_min[3:
0]==4'
counter24su3
.cnth(set_hr[7:
.cntl(set_hr[3:
.en(sethrkey),
assignhrh_equ=(set_hr[7:
4]==hour[7:
4]);
assignhrl_equ=(set_hr[3:
0]==hour[3:
0]);
assignminh_equ=(set_min[7:
4]==minute[7:
assignminl_equ=(set_min[3:
0]==minute[3:
assigntime_equ=(hrh_equ&
hrl_equ&
minh_equ&
minl_equ);
assignalarm_clock=ctrlbell?
time_equ:
1'
modulecomplete_clock
(
inputwireclk50M,
inputwirencr,
inputwiremode,
inputwireoe,
inputwireen,
inputwireadj_min,
inputwireadj_hour,
outputwire[7:
0]qa,
0]qb,
0]qc,
0]qd,
outputwirealarm
wire[7:
0]hour;
0]minute;
0]second;
wirecp;
wire[3:
0]da0;
0]da1;
0]da2;
0]da3;
wirealarm_radio;
wirealarm_clock;
0]set_hr;
0]set_min;
assignda0=mode?
set_min[3:
0]:
(oe?
minute[3:
second[3:
assignda1=mode?
set_min[7:
4]:
minute[7:
second[7:
assignda2=mode?
set_hr[3:
hour[3:
assignda3=mode?
set_hr[7:
hour[7:
assignalarm=alarm_radio||alarm_clock;
top_clocktop1
.hour(hour),
.minute(minute),
.second(second),
.cp(cp),
.adj_min(adj_min),
.adj_hour(adj_hour)
dispdisp1
.clk50M(clk50M),
.HexCode(da3),
.SegmentCode(qa)
dispdisp2
.HexCode(da2),
.SegmentCode(qb)
);
dispdisp3
.HexCode(da1),
.SegmentCode(qc)
dispdisp4
.HexCode(da0),
.SegmentCode(qd)
freqfreq_INST
.rst(~ncr),
.clk1Hz(cp)
radiora1
.alarm_radio(alarm_radio)
bellbe1
.sethrkey(sethrkey),
.setminkey(setminkey),
.ctrlbell(ctrlbell),
.alarm_clock(alarm_clock),
.set_hr(set_hr),
.set_min(set_min)