VHDL参考资料Word文档下载推荐.docx

VHDL参考资料Word文档下载推荐.docx

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Anoutport

canbeupdatedbutnotreadwithinthemodule,carryinginformationoutofthemodule.（Anoutportcannotappearontherighthandsideofasignalassigment.）

Abufferport

likewisecarriesinformationoutofamodule,butcanbebothupdatedandreadwithinthemodule.

Aninoutport

isbidirectionalandcanbebothreadandupdated,withmultipleupdatesourcespossible.

NOTE:

Abufferisstrictlyanoutputport,i.e.canonlybedrivenfromwithinthemodule,whileinoutistrulybidirectionalwithdriversbothwithinandexternaltothemodule.

Example

entitycounteris

port（Incr,Load,Clock:

in 

bit;

Carry:

out 

Data_Out:

bufferbit_vector（7downto0）;

Data_In:

bit_vector（7downto0））;

endcounter;

Genericsallowstaticinformationtobecommunicatedtoablockfromitsenvironmentforallarchitecturesofadesignunit.Theseincludetiminginformation（setup,hold,delaytimes）,partsizes,andotherparameters.

entityand_gateis

port（a,b:

c:

outbit）;

generic（gate_delay:

time:

=5ns）;

endand_gate;

Architecture

Anarchitecturedefinesoneparticularimplementationofadesignunit,atsomedesiredlevelofabstraction.

architecturearch_nameofentity_nameis

... 

declarations...

begin

concurrentstatements 

...

end

Declarationsincludedatatypes,constants,signals,files,components,attributes,subprograms,andotherinformationtobeusedintheimplementationdescription.Concurrentstatementsdescribeadesignunitatoneormorelevelsofmodelingabstraction,includingdataflow,structure,and/orbehavior.

∙BehavioralModel:

Nostructureortechnologyimplied.Usuallywritteninsequential,proceduralstyle.

∙DataflowModel:

Alldatapathsshown,plusallcontrolsignals.

∙StructuralModel:

Interconnectionofcomponents.

VHDLPACKAGES

AVHDLpackagecontainssubprograms,constantdefinitions,and/ortypedefinitionstobeusedthroughoutoneormoredesignunits.Eachpackagecomprisesa"

declarationsection"

inwhichtheavailable（i.e.exportable）subprograms,constants,andtypesaredeclared,anda"

packagebody"

inwhichthesubprogramimplementationsaredefined,alongwithanyinternally-usedconstantsandtypes.Thedeclarationsectionrepresentstheportionofthepackagethatis"

visible"

totheuserofthatpackage.Theactualimplementationsofsubroutinesinthepackagearetypicallynotofinteresttotheusersofthosesubroutines.

Packagedeclarationformat:

packagepackage_nameis

...exportedconstantdeclarations

...exportedtypedeclarations

...exportedsubprogramdeclarations

endpackage_name;

Example:

packageee530is

constantmaxint:

integer:

=16#ffff#;

typearith_mode_typeis（signed,unsigned）;

functionminimum（constanta,b:

ininteger）returninteger;

endee530;

Packagebodyformat:

packagebodypackage_nameis

...exportedsubprogrambodies

...otherinternally-useddeclarations

packagebodyee530is

functionminimum（constanta,b:

integer）returnintegeris

variablec:

integer;

--localvariable

ifa<

bthen

c:

=a;

--aismin

else

=b;

--bismin

endif;

returnc;

--returnminvalue

end;

PackageVisibility

Tomakeallitemsofapackage"

toadesignunit,precedethedesireddesignunitwitha"

use"

statement:

uselibrary_name.package_name.all

A"

statementmayprecedethedeclarationofanyentityorarchitecturewhichistoutilizeitemsfromthepackage.Ifthe"

statementprecedestheentitydeclaration,thepackageisalsovisibletothearchitecture.

User-DevelopedPackages

Compileuser-developedpackagesinyourcurrentworkinglibrary.Tomakeitvisible:

usepackage_name.all;

Note:

'

std'

and'

work'

（yourcurrentworkinglibrary）arethetwodefaultlibraries.TheVHDL'

library'

statementisneededtomakethe'

ieee'

libraryand/oradditionallibrariesvisible.

librarylib_name;

--makelibraryvisible

uselib_name.pkg_name.all;

--makepackagevisible

VHDLStandardPackages

STANDARD-basictypedeclarations（alwaysvisiblebydefault）

TEXTIO-ASCIIinput/outputdatatypesandsubprograms

TomakeTEXTIOvisible:

usestd.textio.all;

IEEEStandard1164Package

Thispackagecontainedinthe'

librarysupportsmulti-valuedlogicsignalswithtypedeclarationsandfunctions.Tomakevisible:

libraryieee;

--VHDLLibrarystmt

useieee.std_logic_1164.all;

Special12-valueddatatypes/functionstointerfacewithQuickSimIIandschematicdiagrams.

librarymgc_portable;

--SpecialMentorGraphicsLibrary

usemgc_portable.qsim_logic.all;

--Quicksimportabledatatypes

VHDLIDENTIFIERS,NUMBERS,STRINGS,ANDEXPRESSIONS

Identifiers

IdentifiersinVHDLmustbeginwithaletter,andmaycompriseanycombinationofletters,digits,andunderscores.NotethatVHDLinternallyconvertsallcharacterstoUPPERCASE.

Examples

Memory1,Adder_Module,Bus_16_Bit

NumericConstants

Numericcontantscanbedefined,andcanbeofanybase（defaultisdecimal）.Numbersmayincludeembeddedunderscorestoimprovereadability.

Format:

base#digits#--basemustbeadecimalnumber

16#9fba# 

（hexadecimal）

2#1111_1101_1011# 

（binary）

16#f.1f#E+2 

（floating-point,exponentisdecimal）

BitStringLiterals

Bitvectorconstantsarearespecifiedasliteralstrings.

x"

ffe"

（12-bithexadecimalvalue）

o"

777"

（9-bitoctalvalue）

b"

1111_1101_1101"

（12-bitbinaryvalue）

ArithmeticandLogicalExpressions

ExpressionsinVHDLaresimilartothoseofmosthigh-levellanguages.Dataelementsmustbeofthetype,orsubtypesofthesamebasetype.Operatorsincludethefollowing:

∙Logical:

and,or,nand,nor,xor,not（forbooleanorbitops）

∙Relational:

=,/=,<

<

=,>

>

=

∙Arithmetic:

+,-,*,/,mod,rem,**,abs

（amodbtakessignofb,arembtakessignofa）

∙Concatenate:

&

（ex.a&

bmakesonearray）

a<

=bnandc;

d:

=g1*g2/3;

Bus_16<

=Bus1_8&

Bus2_8;

VHDLDATATYPES

EachVHDLobjectsmustbeclassifiedasbeingofaspecificdatatype.VHDLincludesanumberofpredefineddatatypes,andallowsuserstodefinecustomdatatypesasneeded.

PredefinedScalarDataTypes（singleobjects）

VHDLStandard:

∙bitvalues:

0'

'

1'

∙booleanvalues:

TRUE,FALSE

∙integervalues:

-（231）to+（231-1）{SUNLimit}

∙naturalvalues:

0tointeger'

high（subtypeofinteger）

∙positivevalues:

1tointeger'

∙charactervalues:

ASCIIcharacters（eg.'

A'

）

∙timevaluesincludeunits（eg.10ns,20us）

IEEEStandard1164（packageieee.std_logic_1164.all）

∙std_ulogicvalues:

U'

'

X'

Z'

W'

H'

L'

-'

'

=uninitialized

=unknown

=weak'

=floating

/'

=don'

tcare

∙std_logicresolved"

std_ulogic"

values

∙X01subtype{'

}ofstd_ulogic

∙X01Zsubtype{'

∙UX01subtype{'

∙UX01Zsubtype{'

}ofstd_ulogic

PredefinedVHDLAggregateDataTypes

∙bit_vectorarray（naturalrange<

>

）ofbit

∙stringarray（naturalrange<

）ofchar

∙textfileof"

string"

IEEEStandard1164AggregateDataTypes

（Frompackage:

ieee.std_logic_1164.all）

∙std_ulogic_vectorarray（naturalrange<

）ofstd_ulogic

∙std_logic_vectorarray（naturalrange<

）ofstd_logic

signaldbus:

bit_vector（15downto0）;

dbus（7downto4）<

="

0000"

;

（4-bitsliceofdbus）

signalcnt:

std_ulogic_vector（1to3）;

variablemessage:

string（0to20）;

User-DefinedEnumerationTypes

Anenumerateddatatypecanbecreatedbyexplicitelylistingallpossiblevalues.

typeopcodesis（add,sub,jump,call）;

--Typewith4values

signalinstruc:

opcodes;

--Signalofthistype

ifinstruc=addthen 

--testforvalue'

add'

Otheruser-definedtypes

Customdatatypescanincludearrays,constrainedandunconstrained,andrecordstructures.

∙Constrainedarray:

Upperandlowerindexesarespecified.

typewordisarray（0to15）ofbit;

∙Unconstrainedarray:

Indexesarespecifiedwhenasignalorvariableofthattypeisdeclared.

typememoryisarray（integerrange<

）ofbit_vector（0to7）;

--atypewhichisanarbitrary-sizedarrayof8-bitvectors

variablememory256:

memory（0to255）;

--a256-bytememoryarray