毕业设计说明书外文文献及翻译Word文件下载.docx

毕业设计说明书外文文献及翻译Word文件下载.docx

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MemoryType

C:

ROM

F:

Flash

P:

OTP

E:

EPROM（fordevelopmentaluse.Therearefewofthese.）

Fa,Fb:

FamilyandFeatures

10,11:

Basic

12,13:

HardwareUART

14:

HardwareUART,HardwareMultiplier

31,32:

LCDController

33:

LCDController,HardwareUART,HardwareMultiplier

41:

43:

LCDController,HardwareUART

44:

Mc:

MemoryCapacity

0:

1kbROM,128bRAM

1:

2kbROM,128bRAM

2:

4kbROM,256bRAM

3:

8kbROM,256bRAM

4:

12kbROM,512bRAM

5:

16kbROM,512bRAM

6:

24kbROM,1kbRAM

7:

32kbROM,1kbRAM

8:

48kbROM,2kbRAM

9:

60kbROM,2kbRAM

Example:

TheMSP430F435isaFlashmemorydevicewithanLCDcontroller,afeaturesnotconsistentlyrepresented（typeofADC,numberoftimers,etc）,andtherearesomeotherinconsistencies（forexample,the33familytheirnumberingscheme.Rather,onceyouchapter1,theMSP430utilizesa16-bitRISCarchitecture,whichiscapableofprocessinginstructionsoneitherbytesorwords.TheCPUisidenticalforallmembersofthe'

430family.Itconsistsofa3-stageinstructionpipeline,instructiondecoding,a16-bitALU,fourdedicated-useregisters,andtwelveworking（orscratchpad）registers.TheCPUisconnectedtoitsmemorythroughtwo16-bitbusses,oneforaddressing,andtheotherfordata.Allmemory,includingRAM,ROM,informationmemory,specialfunctionregisters,andperipheralregistersaremappedintoasingle,contiguousaddressspace.

Thisarchitectureisuniqueforseveralreasons.First,thedesignersatTexasInstrumentsawfullotofspaceforfuturedevelopment.Almostavailablespecialfunctionregistersareimplemented.

Second,thereareplentyofworkingregisters.Afteryearsofbemuchmoreefficient,especiallyinthemostothersmallprocessors.But,beyondthat,thisarchitectureissimple,efficientandclean.Therearetwobusses,asinglelinearmemoryspace,arathervanillaprocessorcore,andallperipheralsarememory-mapped.

CPUFeatures

TheALU

The'

430processorincludesaprettytypicalALU（arithmeticlogicunit）.TheALU,subtraction,comparisonandlogical（AND,OR,XOR）operations.ALUoperationscanaffecttheoverflow,zero,negative,andcarryflags.Thealldevices,isimplementedasaperipheraldevice,andisnotpartoftheALU（seeChapter6）.

WorkingRegisters

430givesthedevelopertwelve16-bitworkingregisters,R4throughR15.（R0throughR3areusedforotherfunctions,asdescribedlater.）Theyareusedforregistermodeoperations（seeAddressingModes,Chapter8）,whicharemuchmoreefficientthanoperationswhichrequirememoryaccess.Someguidelinesfortheiruse:

Usetheseregistersasmuchaspossible.Anyvariablewhichisaccessedoftenshouldresideinoneoftheselocations,forthesakeofefficiency.

Generallyspeaking,youmayselectanyoftheseregistersforanypurpose,eitherdataoraddress.However,somedevelopmenttoolswillreserveR4andR5fordebuginformation.Differentcompilerswillusetheseregistersindifferentfashions,aswell.Understandyourtools.

Beconsistentaboutuseoftheworkingregisters.Clearlydocumenttheiruse.Iabout8monthsago,thatperformsextensiveoperationsonR8,R9,andR15.Unfortunately,Idon'

tknowtodaywhatthevaluesinR8,R9andR15represent.ThiswascodeIwrotetoquicklyvalidateanalgorithm,ratherthanproductioncode,soIdidn'

tdocumentitsufficiently.Now,itisrelativegibberish.Don'

tletthistoyou.Nomatterasconstantgenerators,sothatregistermodemaybeusedinsteadofimmediatemodeforsomecommonconstants.（R2isadualuseregister.ItservesastheStatusRegister,aswell.）Generatedconstantsincludesomecommonsingle-bitvalues（0001h,0002h,0004h,and0008h）,zero（0000h）,andanall1sfield（0FFFFh）.GenerationisbasedontheW（S）valueintheinstructionword,andisdescribedbythetablebelow.

W（S）valueinR2valueinR3

00————0000h

01（0）（absolutemode）0001h

100004h0002h

110008h0FFFFh

ProgramCounter

TheProgramCounterislocatedinR0.Sinceindividualmemorylocationaddressesare8-bit,butallinstructionsare16bit,thePCisconstrainedtoevennumbers（i.e.theLSBofthePCisalwayszero）.Generallyspeaking,itisbesttoavoiddirectmanipulationofthePC.Oneexceptiontothisruleofthumbistheimplementationofaswitch,wherethecodejumpstoaspot,dependentonagivenvalue.（I.e.,ifvalue=0,jumptolocation0,ifvalue=1,jumptolocation1,etc.）ThisprocessisshowninExample3.1.

Example3.1SwitchStatementviaManualPCControl

Movvalue,R15;

puttheswitchvalueintoR15

CmpR15,#8;

rangechecking

Jgeoutofrange;

ifR15>

7,donotusePCswitch

Cmp#0,R15;

morerangechecking

Jnoutofrange;

RlaR15;

multiplyR15bytwo,sincePCisalwayseven

doubleR15again,sincesymbolicjmpis2wordslong

AddR15,PC;

PCgoestoproperjump

Jmpvalue0

Jmpvalue1

Jmpvalue2

Jmpvalue3

Jmpvalue4

Jmpvalue5

Jmpvalue6

Jmpvalue7

Outofrange

JmpRangeError

Thisisarelativelycommonapproach,andmostCcompilerswillimplementswitchstatementswithsomethingsimilar.Whenimplementingthismanually（i.e.,inassemblylanguage）,theprogrammerneedstokeepseveralthingsinmind:

Alwaysdoproperrangechecking.Intheexample,wecheckedforconditionsoutsidebothendsofthevalidrange.Ifthisisnotperformedcorrectly,thecodecanjumptoanunintendedlocation.

Paycloseattentiontotheaddressingmodesofthejumpstatements.TheseconddoublingofR15,priortotheaddstatement,isaddedbecausethejumpstatementrequirestwowordswhensymbolicmodeaddressingisused.

Becarefulthatnoneofyourinterrupttheexample）.IftheinterruptprocedureistopushtheregistertothestackatthebeginningoftheISR,andtopoptheregisterattheendoftheISR.（SeeExample3.2.）

Example3.2PushPopCombinationinISR

Timer_A_Hi_Interrupt

PushR12;

WewilluseR12

MovP1IN,R12;

useR12asweplease

RlaR12

RlaR12

MovR12&

BAR;

DonewithR12

PopR12;

RestorepreviousvaluetoR12

Reti;

returnfrominterrupt

ORG0FFF0h

DWTimer_A_Hi_Interrupt

StatusRegister

TheStatusRegisterisimplementedinR2,andiscomprisedofvarioussystemflags.Theflagsarealldirectlyaccessiblebycode,andallbutthreeofthemarechangedautomaticallybytheprocessoritself.The7mostsignificantbitsareundefined.ThebitsoftheSRare:

•TheCarryFlag（C）

Location:

SR（0）（theLSB）

Function:

Identifieswhenanoperationresultsinacarry.Canbesetorclearedbysoftware,orautomatically.

1=Carryoccurred

0=Nocarryoccurred

•TheZeroFlag（Z）

Location:

SR

（1）

Identifieswhenanoperationresultsinazero.Canbesetorclearedbysoftware,orautomatically.

1=Zeroresultoccurred

0=Nonzeroresultoccurred

•TheNegativeFlag（N）

SR

（2）

Identifieswhenanoperationresultsinanegative.Canbesetorclearedbysoftware,orautomatically.ThisflagreflectsthevalueoftheMSBoftheoperationresult（Bit7forbyteoperations,andbit15forwordoperations）.

1=Negativeresultoccurred

0=Positiveresultoccurred

•TheGlobalInterruptEnable（GIE）

Location:

SR（3）

Function:

Enablesordisablesallmaskableinterrupts.Canbesetorclearedbysoftware,orautomatically.Interruptsautomaticallyresetthisbit,andtheretiinstructionautomaticallysetsit.

1=InterruptsEnabled

0=InterruptsDisabled

•TheCPUoffbit（CPUOff）

SR（4）

EnablesordisablestheCPUcore.Canbeclearedbysoftware,andisresetbyenabledinterrupts.Noneofthememory,peripherals,orclocksareaffectedbythisbit.Thisbitisusedasapowersavingfeature.

1=CPUison

0=CPUisoff

•TheOscillatoroffbit（OSCOff）

SR（5）

Enablesordisablesthecrystaloscillatorcircuit（LFXT1）.Canbeclearedbysoftware,andisresetbyenabledexternalinterrupts.OSCOffshutsdowneverything,includingperipherals.RAMandregistercontentsarepreserved.Thisbitisu