VHDL多功能数字钟实现程序.docx
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VHDL多功能数字钟实现程序
1、程序包模块
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
USEIEEE.STD_LOGIC_UNSIGNED.ALL;
PACKAGEpacIS
procedureadd_year（oldyear0,oldyear1:
instd_logic_vector;
signalnewyear0:
outstd_logic_vector;
signalnewyear1:
outstd_logic_vector）;
procedureadd_month（oldmonth0,oldmonth1:
instd_logic_vector;
signalnewmonth0:
outstd_logic_vector;
signalnewmonth1:
outstd_logic_vector）;
proceduresub_month（oldmonth0,oldmonth1:
instd_logic_vector;
signalnewmonth0:
outstd_logic_vector;
signalnewmonth1:
outstd_logic_vector）;
proceduresub_year（oldyear0,oldyear1:
instd_logic_vector;
signalnewyear0:
outstd_logic_vector;
signalnewyear1:
outstd_logic_vector）;
procedureFeb_add_day（oldday0,oldday1:
instd_logic_vector;
Ty0:
instd_logic_vector（1downto0）;
Ty1:
instd_logic;
signalnewday0:
outstd_logic_vector;
signalnewday1:
outstd_logic_vector）;
procedureFeb_sub_day（oldday0,oldday1:
instd_logic_vector;
Ty0:
instd_logic_vector（1downto0）;
Ty1:
instd_logic;
signalnewday0:
outstd_logic_vector;
signalnewday1:
outstd_logic_vector）;
procedureoddmonth_add_day（oldday0,oldday1:
instd_logic_vector;
signalnewday0:
outstd_logic_vector;
signalnewday1:
outstd_logic_vector）;
procedureoddmonth_sub_day（oldday0,oldday1:
instd_logic_vector;
signalnewday0:
outstd_logic_vector;
signalnewday1:
outstd_logic_vector）;
procedureevenmonth_add_day（oldday0,oldday1:
instd_logic_vector;
signalnewday0:
outstd_logic_vector;
signalnewday1:
outstd_logic_vector）;
procedureevenmonth_sub_day（oldday0,oldday1:
instd_logic_vector;
signalnewday0:
outstd_logic_vector;
signalnewday1:
outstd_logic_vector）;
procedureaddsec_addmin（oldtime0,oldtime1:
instd_logic_vector;
signalnewtime0:
outstd_logic_vector;
signalnewtime1:
outstd_logic_vector）;
proceduresubsec_submin（oldtime0,oldtime1:
instd_logic_vector;
signalnewtime0:
outstd_logic_vector;
signalnewtime1:
outstd_logic_vector）;
procedureaddhour（oldhour0,oldhour1:
instd_logic_vector;
signalnewhour0:
outstd_logic_vector;
signalnewhour1:
outstd_logic_vector）;
proceduresubhour（oldhour0,oldhour1:
instd_logic_vector;
signalnewhour0:
outstd_logic_vector;
signalnewhour1:
outstd_logic_vector）;
endpac;
packagebodypacis
procedureadd_year（oldyear0,oldyear1:
instd_logic_vector;
signalnewyear0:
outstd_logic_vector;
signalnewyear1:
outstd_logic_vector）is
begin
if（oldyear0="1001"andoldyear1/="1001"）then
newyear0<="0000";newyear1<=oldyear1+'1';
elsenewyear0<=oldyear0+'1';
endif;
if（oldyear0="1001"andoldyear1="1001"）then
newyear0<="0000";newyear1<="0000";
endif;
endadd_year;
procedureadd_month（oldmonth0,oldmonth1:
instd_logic_vector;
signalnewmonth0:
outstd_logic_vector;
signalnewmonth1:
outstd_logic_vector）is
begin
if（oldmonth0="0010"andoldmonth1="0001"）then
newmonth0<="0001";newmonth1<="0000";
elsifoldmonth0="1001"then
newmonth0<="0000";newmonth1<=oldmonth1+'1';
elsenewmonth0<=oldmonth0+'1';
endif;
endadd_month;
proceduresub_year（oldyear0,oldyear1:
instd_logic_vector;
signalnewyear0:
outstd_logic_vector;
signalnewyear1:
outstd_logic_vector）is
begin
ifoldyear0="0000"then
ifoldyear1="0000"then
newyear1<="1001";
elsenewyear1<=oldyear1-'1';
endif;
newyear0<="1001";
elsenewyear0<=oldyear0-'1';
endif;
endsub_year;
proceduresub_month（oldmonth0,oldmonth1:
instd_logic_vector;
signalnewmonth0:
outstd_logic_vector;
signalnewmonth1:
outstd_logic_vector）is
begin
if（oldmonth0="0001"andoldmonth1="0000"）then
newmonth0<="0010";newmonth1<="0001";
elsif（oldmonth0="0000"andoldmonth1="0001"）then
newmonth0<="1001";newmonth1<=oldmonth1-'1';
elsenewmonth0<=oldmonth0-'1';
endif;
endsub_month;
procedureFeb_add_day（oldday0,oldday1:
instd_logic_vector;
Ty0:
instd_logic_vector（1downto0）;
Ty1:
instd_logic;
signalnewday0:
outstd_logic_vector;
signalnewday1:
outstd_logic_vector）is
begin--平年2月天数加
if（oldday0="1000"andoldday1="0010"）then
if（（Ty1='0'andTy0="00"）or（Ty1='1'andTy0="10"））then
newday0<=oldday0+'1';
else
newday0<="0001";newday1<="0000";
endif;
elsif（oldday0="1001"andoldday1="0010"）then
newday0<="0001";newday1<="0000";
elsif（oldday0="1001"）then
newday0<="0000";newday1<=oldday1+'1';
elsenewday0<=oldday0+'1';
endif;
endFeb_add_day;
procedureFeb_sub_day（oldday0,oldday1:
instd_logic_vector;
Ty0:
instd_logic_vector（1downto0）;
Ty1:
instd_logic;
signalnewday0:
outstd_logic_vector;
signalnewday1:
outstd_logic_vector）is
begin--平年2月减
if（oldday0="0000"oroldday0="0001"）andoldday1="0000"then
if（（Ty1='0'andTy0="00"）or（Ty1='1'andTy0="10"））then
newday0<="1001";newday1<="0010";
elsenewday0<="1000";newday1<="0010";
endif;
elsif（oldday0="0000"andoldday1/="0000"）then
newday0<="1001";newday1<=oldday1-'1';
elsenewday0<=oldday0-'1';
endif;
endFeb_sub_day;
procedureoddmonth_add_day（oldday0,oldday1:
instd_logic_vector;
signalnewday0:
outstd_logic_vector;
signalnewday1:
outstd_logic_vector）is
begin--大月加
if（oldday0="0001"andoldday1="0011"）then
newday0<="0001";newday1<="0000";
elsifoldday0="1001"then
newday0<="0000";newday1<=oldday1+'1';
elsenewday0<=oldday0+'1';
endif;
endoddmonth_add_day;
procedureoddmonth_sub_day（oldday0,oldday1:
instd_logic_vector;
signalnewday0:
outstd_logic_vector;
signalnewday1:
outstd_logic_vector）is
begin--大月减
if（oldday0="0001"oroldday0="0000"）andoldday1="0000"then
newday0<="0001";newday1<="0011";
elsifoldday0="0000"andoldday1/="0000"then
newday0<="1001";newday1<=oldday1-'1';
elsenewday0<=oldday0-'1';
endif;
endoddmonth_sub_day;
procedureevenmonth_add_day（oldday0,oldday1:
instd_logic_vector;
signalnewday0:
outstd_logic_vector;
signalnewday1:
outstd_logic_vector）is
begin--小月加
if（oldday0="0000"andoldday1="0011"）then
newday0<="0001";newday1<="0000";
elsifoldday0="1001"then
newday0<="0000";newday1<=oldday1+'1';
elsenewday0<=oldday0+'1';
endif;
endevenmonth_add_day;
procedureevenmonth_sub_day（oldday0,oldday1:
instd_logic_vector;
signalnewday0:
outstd_logic_vector;
signalnewday1:
outstd_logic_vector）is
begin--小月减
if（oldday0="0001"oroldday0="0000"）andoldday1="0000"then
newday0<="0000";newday1<="0011";
elsif（oldday0="0000"andoldday1/="0000"）then
newday0<="1001";newday1<=oldday1-'1';
elsenewday0<=oldday0-'1';
endif;
endevenmonth_sub_day;
procedureaddsec_addmin（oldtime0,oldtime1:
instd_logic_vector;
signalnewtime0:
outstd_logic_vector;
signalnewtime1:
outstd_logic_vector）is
begin--秒、分加
if（oldtime0="1001"）then
newtime0<="0000";
if（oldtime1="0101"）then
newtime1<="0000";
elsenewtime1<=oldtime1+'1';
endif;
elsenewtime0<=oldtime0+'1';
endif;
endaddsec_addmin;
proceduresubsec_submin（oldtime0,oldtime1:
instd_logic_vector;
signalnewtime0:
outstd_logic_vector;
signalnewtime1:
outstd_logic_vector）is
begin--秒、分减
if（oldtime0="0000"）then
newtime0<="1001";
if（oldtime1="0000"）then
newtime1<="0101";
elsenewtime1<=oldtime1-'1';
endif;
elsenewtime0<=oldtime0-'1';
endif;
endsubsec_submin;
procedureaddhour（oldhour0,oldhour1:
instd_logic_vector;
signalnewhour0:
outstd_logic_vector;
signalnewhour1:
outstd_logic_vector）is
begin--时加
if（oldhour0="1001"）then
newhour0<="0000";
newhour1<=oldhour1+'1';
elsenewhour0<=oldhour0+'1';
endif;
if（oldhour0="0011"andoldhour1="0010"）then
newhour0<="0000";newhour1<="0000";
endif;
endaddhour;
proceduresubhour（oldhour0,oldhour1:
instd_logic_vector;
signalnewhour0:
outstd_logic_vector;
signalnewhour1:
outstd_logic_vector）is
begin--时减
if（oldhour0="0000"）then
newhour0<="1001";
newhour1<=oldhour1-'1';
elsenewhour0<=oldhour0-'1';
endif;
if（oldhour0="0000"andoldhour1="0000"）then
newhour0<="0011";newhour1<="0010";
endif;
endsubhour;
endpac;
2、顶层模块
libraryIEEE;
useIEEE.STD_LOGIC_1164.ALL;
useIEEE.STD_LOGIC_ARITH.ALL;
useIEEE.STD_LOGIC_UNSIGNED.ALL;
--Uncommentthefollowinglinestousethedeclarationsthatare
--providedforinstantiatingXilinxprimitivecomponents.
--libraryUNISIM;
--useUNISIM.VComponents.all;
entitytimekeeperis
port（up,setpin,upclk,f1000:
instd_logic;
pass,stop,enable:
instd_logic;
a0,a1,b0,b1,c0,c1,d0:
outstd_logic_vector（3downto0）;
z:
outstd_logic;
sp:
outstd_logic）;
endtimekeeper;
architectureBehavioraloftimekeeperis
componentfenpinport（f1000:
instd_logic;
second_wave:
bufferstd_logic）;
endcomponent;
componenth_m_sport（clk0,clk1,ce:
instd_logic;
sec0,sec1:
bufferstd_logic_vector（3downto0）;
set:
instd_logic_vector（3downto0）;
up:
instd_logic;
min0,min1:
bufferstd_logic_vector（3downto0）;
hour0,hour1:
bufferstd_logic_vector（3downto0）;
z,ov:
outstd_logic）;
endcomponent;
componentdateport（clk0,clk1,ce:
instd_logic;
set:
instd_logic_vector（3downto0）;
up:
instd_logic;
mon0,mon1,year0,year1:
instd_logic_vector（3downto0）;
date0,date1:
bufferstd_logic_vector（3downto0）;
ov:
outstd_logic）;
endcomponent;
componentyear_monport（clk0,clk1,ce:
instd_logic;
set:
std_logic_vector（3downto0）;
up:
instd_logic;
mon0,mon1:
bufferstd_logic_vector（3downto0）;
year0,year1:
bufferstd_logic_vector（3downto0））;
endcomponent;
componentledport（set:
std_logic_vector（3downto0）;
sec0,sec1,min0,min1,hour0,hour1:
instd_logic_vector（3downto0）;
a0,a1,b0,b1,c0,c1:
outstd_logic_vector（3downto0）;
nm1,nm0,nh1,nh0:
std_logic_vector（3downto0）;
date0,date1,mon0,mon1,year0,year1:
instd_logic_vector（3downto0））;
endcomponent;
componentalarmport（clk1,ce:
instd_logic;
set:
instd_logic_vector（3downto0）;
up:
instd_logic;
min0,min1:
bufferstd_logic_vector（3downto0）:
="0000";
hour0,hour1:
bufferstd_logic_vector（3downto0）:
="0000"）;
endcomponent;
componentwe
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