大连交通大学coa考试题3.docx

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大连交通大学coa考试题3

I.Inmulti-processorsystem,MEMIprotocolisusedtosolvetheproblemofcachecoherence,Accordingtothegivenfigure,answerthefollowingquestions.

InitialSnoopy

1.Thisisthecaseof________________.

2.Pleasefinishdrawingthefigure

3.Withthiscase,pleasefillbestanswersintothefollowingtabel

Thestatesinbegin

Thestatesinend

Initial

Snoopy

Initial

Snoopy

1ThisisthecaseofReadMiss.

3.

Thestatesinbegin

Thestatesinend

Initial

Snoopy

Initial

Snoopy

I

I

Initreadfrommemory,

E

I

I

S

Initreadfrommemory

S

S

I

E

Initreadfrommemory

S

S

I

M

Snoopywritebackdatatomemory,Initreadfrommemory

S

S

II.Thefollowinginstruction:

LOADAC,X

----TransferthecontentoflocationXinmemorytoAC

Question:

1.Whichaddressingmodeisincludedinthisinstruction?

2.Pleasedrawthefigureofitsaddressingmode.

3.Writedownallthemicro-operationsandthecontrolsignals.

1.

directaddressing

2.

3.Fetchcycle:

T1:

(PC)MAR

T2:

(MAR)MEMORY

READMEMORY

T3:

MEMORYMBR

T4:

(MBR)IR

(PC)+1PC

EXECUTECYCLE:

T1:

AD(MBR)MAR

T2:

(MAR)MEMORY

READMEMORY

T3:

MEMORYMBR

T4:

(MBR)AC

III.Afour-waysetassociativecachehas64kwordsandalinesizeof8words,Mainmemoryhas4Gwords.

Questions:

1.Whatdoesfour-waysetassociativemappingmean?

2.Howtodetermineacachehit/miss.

3.Showtheaddressmappingformat.

4.Whereinthecacheisthedatafrommemorylocation1FDB9753Hand1ABCD419H?

(whenreadfrommemory).

1.

Agivenblockinmemoryismappedintoanylineoffourlinesinafixedset.

2.Coparingtagdeterminescachehitonorhitmiss

3.memorysize=4Gwords=232lengthofRA=32-bit

linesize=8words=23wordsWord#=3-bit

thenumberofsets=64Kword/8word/4=2k=211Set#=11-bit

tag=32-11-3=18-bit

TagSet#Word#

18

11

3

4.1FDB9753H

=00,0111,1111,0110,1110010,1110,1010011B

07F6EH2EAH

Set#=2EAHTag=07F6EH

1ABCD419H

=00,0110,1010,1111,0011010,1000,0011001B

06AF3H283H

Set#=283HTag=06AF3H

IV.Forthe8-bitdata1100,1011.Supposewhenthedataisreadfrommemory,thecheckbitsarecalculatedtobe0011.

Questions:

1.Pleasesetuptruevaluetabletoarrangedatabitsandcheckbits

2.Pleasemakeouttherelationshipofcheckbitsanddatabits.

3.Whatarethecheckbitsstoredwithdata

4.Whatishammingcodetobestoredinmemory

5.Whatisthedatathatwasreadfrommemory.

1100,1011

BitPosition

PositionNumber

Checkbit

Databit

12

1100

D8

1

11

1011

D7

1

10

1010

D6

0

9

1001

D5

0

8

1000

C8

0

7

0111

D4

1

6

0110

D3

0

5

0101

D2

1

4

0100

C4

1

3

0011

D1

1

2

0010

C2

1

1

0001

C1

0

2.

C1=D1⊕D2⊕D4⊕D5⊕D7

C2=D1⊕D3⊕D4⊕D6⊕D7

C4=D2⊕D3⊕D4⊕D8

C8=D5⊕D6⊕D7⊕D8

3.C1=1⊕1⊕1⊕0⊕1=0

C2=1⊕0⊕1⊕0⊕1=1

C4=1⊕0⊕1⊕1=1

C8=0⊕0⊕1⊕1=0

4.110001011110

5.SYNDROMWORD:

0110

0011

-----------------

0101=5

SoD2iswrong,thedatathatwasreadfrommemoryis1100,1001

V.

1.CacheisusedtosolvetheproblemofspeedbetweenCPUandmainmemory

2.VonNeumannmachinehadtobeprogrammedmanuallyinhardware.

3.Abytealwaysis8bits,butthelengthofawordisunfixed.

4.ProgramcounterisaregisterinCPU,italwayspointtothetopofstack.

5.Booth’salgorithmisusedforsign-magnitudemultiplication.

6.Theworstfactorthatlimitstheperformanceofinstructonpipeliningisconditionalbranchinstruction.

7.Write-backpolicymeanswriteoperantiontomainmemoryaswellastocache

8.Accumulatoristhepartofarithmeticandlogicunit.

9.Inmemorysystem,therearefouraccessmethods,cacheisrandomaccess.

10.TheremainderissavedwhileexecutingISR.

YNYNNYNNNY

VI.

1.Whichdoesn’tbelongtosystembus?

________

A.addressbusB.powerline

C.databusD.controlbus

2.WhichansweraboutHammingcodeisnottrue?

A.thepurposeofusinghammingcodeonlyisdetectingone-biterror.

B.usinghamingcodecandirectlycorrecttwo-biterror.

C.hammingcodeisaSingle-Error-Correctingcode.

D.hammingcodeisaMultiple-Error-Correctingcode.

3.Assumea10-driveRAIDconfiguration.InRAID1level,storagedensityis____

A.90%B.80%C.60%D.50%

4.ComparedwithRAID4theadvantageofRAID5is________.

A.Eachdiskoperateindependently.

B.Largestrips

C.Parityisstripedacrossalldisks

D.Dataonfiaileddivecanbereconstructed.

5.Ininterruptprocessing,CPUsendsacknowledgementofinterrut.ThemoreimportantreasonofCPU’sacknowledgementis________.

A.toletCPUgetthevectorfromdatabus

B.tolettheI/Omoduleremoverequestsignal

C.bothAandB

D.otheraims

6.WhenanI/OdevicecompletesanI/Ooperationininterrupt-drivenI/O,thefollowingsequenceofhardwareeventsoccurs________.

①I/OmoduleissuesaninterruptsignaltoCPU

②CPUsignalacknowledgmentofinterrupt

③CPUfinishesexecutionofcurrentinstruction

④CPUloadsnewPCvaluebasedoninterrupt

⑤CPUsavePSWandPCtostack

A.①②③④⑤B.①③⑤②④

C.①③⑤④②D.①③②⑤④

7.ComparingwithprogrammedI/O,interrupt-drivenI/OfurtherraisestheusagerateofCPUoperations,because_____.

A.itisn’tnecessaryforCPUtosaveandrestorescene

B.itisn’tnecessaryforCPUtointervenethedatatransfer

C.itisn’tnecessaryforCPUtoreadandcheckstatusrepeatedly

D.bothAandB

8.Whichisthefollowingdescriptionaboutoverflownottrue?

______

A.Overflowoccurssometimeinaddandsubtractarithmeticoperation.

B.Overflowandcarriageisnotdifferent

C.Overflowcanoccurwhetherornotthereiscarry

D.Overflowdoesnotoccurinmultiplicationoperationofunsignedbinaryinteger

9.An8-bittwoscomplement00010011isnegated,thenchangedtoa16-bitthatequalto_______.

A.1000000000010011B.0000000000010011

C.1111111111101101D.1111111111101100

10.Comparedwithregisterindirectaddressingmode,thedisadvantageofindirectaddressingmodeis______.

A.LargeaddressspaceB.Multiplememoryreferences

C.LimitaddressspaceD.Lessmemoryaccess

11.RISCrejects________.

A.few,simpleaddressingmodes

B.alimitedandsimpleinstrtuctionsets

C.fewnumberofregisters

D.few,simpleinstructionformats

12.Attheendoffetchcyclemicro-operations,theMARcontains_______.

A.instructionB.addressofinstruction

C.operandD.addressofoperand

13.Controlunitusesomeinputsignalstoproducecontrolsignalsthatopenthegatesofinformationpathsandletthemicro-operationsimplement,WhichisNOTtheinputsignalofcontrolunit?

A.clockandflagsB.opcodeintheinstructionregister

C.interruptrequestsignalD.signalsthatcausedatamovement

14.TheSymmetricMulti-Processor(SMP)systemistightlycoupledby______.

A.high-speeddata-linkanddistributedmemory

B.sharedRAIDsandhigh-speeddata-link

C.interconnectnetworkanddistributedmemory

D.distributedcachesandsharedmemory

15.Thefourstatesof“MESI”are______.

A.Modified,Exclusive,SharedandInclusive

B.Modified,Exclusive,SharedandInvalid

C.Modified,Expected,SharedandInterrupted

D.Moved,Exchanged,SharedandInvalid

16.“Word”lengthmeans________.

A.thenumberofbinarycodeinastorageunit

B.acombinationofbinarycodeinastorageunit

C.thenumberofstorageunits

D.thelengthofanoperand

17.Dataprocessingisprovidedby_____whicharethebasicelementsofcomputer.

A.gatesB.memorycellsC.ALUD.CPU

18.Wordlengthofacomputeris32-bit,itsstoragecpacityis64Kbyte.

Whatisaddressablerange?

___________

A.16KBB.16KC.32KD.32KB

19.Whichistruethefollowingstatements?

______

A.RAMisreadableandwriteable;datawillbemaintainedwhenpowerdown

B.RAMisavolatile,butstaticRAMisnon-volatile

C.EPROMiswritten,soitisarandowaccessmemory

D.EPROMiswritten,butisisn’trandomaccessmemory

20.Onamovableheadsystem,thetimeittakesforthebeginningofthesectortoreachtheheadisknownas

A.rotationaldelayB.seektimeC.transfertimeD.accesstime

21.RAIDlevels2and3makeuseofa______technique.

A.parallelaccessB.randomaccess

C.directaccessD.independentaccess

22.Whichistruethefollowingstatements?

__________

A.interrupthasinterruptrequest,butDMAhasn’tinterruptrequest.

B.interruptandDMAhaveinterruptrequests,buttheiraimsaren’tsame.

C.DMAhasinterruptrequst,butinterrupthasn’tinterruptrequest.

D.interruptandDMAhaveinterruptreuests,andtheiraimsaresame.

23.Intwo’scomplement,twonegativeintegersareadded,whendoesoverflowoccurs?

______

A.thesignofresultis0B.theresulthasacarrybit

C.theresulthasacarrybitD.can’tdetermine

24.Inbaseregisteraddressing,theeffectiveaddressofoperandis______.

A.(PC)+displacementB.(baseregister)+displacement

C.addressfieldD.register

25.______issimilartodirectaddressing,butoperandisheldinregisternamedinaddressfieldoftheinstruction.

A.displacementaddressingB.stackaddressing

C.registerindirectaddressingD.register

26.Inaninstruction,thenumberofaddressisone,thesecondaddressisimplicit,usuallyis_____.

A.PCB.SPC.ACD.IR

27.Ifaninstructionincludesfoursub-cycles,a(n)______occursaferexecutesub-cycle.

A.fetchsub-cycleB.indirectsub-cycle

C.interruptsub-cycleD.can[tdetermine

28.Onaddressmappingofcache,anyblockofmainmemorycanbemappedtoanylineofcacheitit______.

A.associativemappingB.directmapping

C.setassociativemappingD.randommapping

29.Theexecutionspeedofaddressingmodes:

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