vhdl语言例程集锦.docx
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vhdl语言例程集锦
vhdl语言例程集锦
ExamplesofVHDLDescriptions
AdvancedElectronicDesignAutomation
ExamplesofVHDLDescriptions
Author:
IanElliottofNorthumbriaUniversity
ThisfilecontainsaselectionofVHDLsourcefileswhichservetoillustratethediversityandpowerofthelanguagewhenusedtodescribevarioustypesofhardware.Theexamplesrangefromsimplecombinationallogic,describedin
termsofbasiclogicgates,tomorecomplexsystems,suchasabehaviouralmodelofamicroprocessorandassociatedmemory.AlloftheexamplescanbesimulatedusinganyIEEEcompliantVHDLsimulatorandmanycanbe
synthesisedusingcurrentsynthesistools.
Usethehierarchicallinksbelowtonavigateyourwaythroughtheexamples:
lCombinationalLogic
lCounters
lShiftRegisters
lMemory
lStateMachines
lRegisters
lSystems
lADCandDAC
lArithmetic
CombinationalLogic
lExclusive-ORGate（Dataflowstyle）
lExclusive-ORGate（Behaviouralstyle）
lExclusive-ORGate（Structuralstyle）
lMiscellaneousLogicGates
lThree-inputMajorityVoter
lMagnitudeComparator
lQuad2-inputNand（74x00）
lBCDtoSevenSegmentDecoder
lDual2-to-4Decoder
lOctalBusTransceiver
lQuad2-inputOR
l8-bitIdentityComparator
lHammingEncoder
lHammingDecoder
l2-to-4DecoderwithTestbenchandConfiguration
lMultiplexer16-to-4usingSelectedSignalAssignmentStatement
lMultiplexer16-to-4usingConditionalSignalAssignmentStatement
lMultiplexer16-to-4usingif-then-elsif-elseStatement
lM68008AddressDecoder
lHighestPriorityEncoder
lN-inputANDGate
Counters
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ExamplesofVHDLDescriptions
lCounterusingaConversionFunction
lGeneratedBinaryUpCounter
lCounterusingMultipleWaitStatements
lSynchronousDownCounterwithParallelLoad
lMod-16CounterusingJKFlip-flops
lPseudoRandomBitSequenceGenerator
lUniversalCounter/Register
ln-BitSynchronousCounter
ShiftRegisters
lUniversalShiftRegister/Counter
lTTL164ShiftRegister
lBehaviouraldescriptionofan8-bitShiftRegister
lStructuralDescriptionofan8-bitShiftRegister
Memory
lROM-basedWaveformGenerator
lAFirst-inFirst-outMemory
lBehaviouralmodelofa16-word,8-bitRandomAccessMemory
lBehaviouralmodelofa256-word,8-bitReadOnlyMemory
StateMachines
lClassic2-ProcessStateMachineandTestBench
lStateMachineusingVariable
lStateMachinewithAsynchronousReset
lPatternDetectorFSMwithTestBench
lStateMachinewithMooreandMealyoutputs
lMooreStateMachinewithExplicitStateencoding
lMealyStateMachinewithRegisteredOutputs
lMooreStateMachinewithConcurrentOutputLogic
Systems
lPelicanCrossingController
lSimpleMicroprocessorSystem
lBoothMultiplier
lLotteryNumberGenerator
lDigitalDelayUnit
lChessClock
ADCandDAC
lPackagedefiningaBasicAnaloguetype
l16-bitAnaloguetoDigitalConverter
l16-bitDigitaltoAnalogueConverter
l8-bitAnaloguetoDigitalConverter
l8-bitUnipolarSuccessiveApproximationADC
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ExamplesofVHDLDescriptions
Arithmetic
l8-bitUnsignedMultiplier
ln-bitAdderusingtheGenerateStatement
lAVarietyofAdderStyles
lBoothMultiplier
Registers
lUniversalRegister
lOctalD-TypeRegisterwith3-StateOutputs
lQuadD-TypeFlip-flop
l8-bitRegisterwithSynchronousLoadandClear
UniversalRegister
Description-Thisdesignisauniversalregisterwhichcanbeusedasastraightforwardstorageregister,abi-directionalshiftregister,anupcounterandadowncounter.Theregistercanbeloadedfromasetofparalleldatainputs
andthemodeiscontrolledbya3-bitinput.The'termcnt'（terminalcount）outputgoeshighwhentheregistercontainszero.
LIBRARYieee;
USE
USE
ENTITYunicntrIS
GENERIC（n:
Positive:
=8）;--sizeofcounter/shifter
PORT（clock,serinl,serinr:
INStd_logic;--serialinputs
mode:
INStd_logic_vector（2DOWNTO0）;--modecontrol
datain:
INStd_logic_vector（（n-1）DOWNTO0）;--parallelinputs
dataout:
OUTStd_logic_vector（（n-1）DOWNTO0）;--paralleloutputs
termcnt:
OUTStd_logic）;--terminalcountoutput
ENDunicntr;
ARCHITECTUREv1OFunicntrIS
SIGNALint_reg:
Std_logic_vector（（n-1）DOWNTO0）;
BEGIN
main_proc:
PROCESS
BEGIN
WAITUNTILrising_edge（clock）;
CASEmodeIS
--reset
WHEN"000"=>int_reg<=（OTHERS=>'0'）;
--parallelload
WHEN"001"=>int_reg<=datain;
--countup
WHEN"010"=>int_reg<=int_reg+1;
--countdown
WHEN"011"=>int_reg<=int_reg-1;
--shiftleft
WHEN"100"=>int_reg<=int_reg（（n-2）DOWNTO0）&serinl;
--shiftright
WHEN"101"=>int_reg<=serinr&int_reg（（n-1）DOWNTO1）;
--donothing
WHENOTHERS=>NULL;
ENDCASE;
ENDPROCESS;
det_zero:
PROCESS（int_reg）--detectswhencountis0
BEGIN
termcnt<='1';
FORiINint_reg'RangeLOOP
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ExamplesofVHDLDescriptions
IFint_reg（i）='1'THEN
termcnt<='0';
EXIT;
ENDIF;
ENDLOOP;
ENDPROCESS;
--connectinternalregistertodataoutport
dataout<=int_reg;
ENDv1;
OctalD-TypeRegisterwith3-StateOutputs
SimplemodelofanOctalD-typeregisterwiththree-stateoutputsusingtwoconcurrentstatements.
LIBRARYieee;
USE
ENTITYttl374IS
PORT（clock,oebar:
INstd_logic;
data:
INstd_logic_vector（7DOWNTO0）;
qout:
OUTstd_logic_vector（7DOWNTO0））;
ENDENTITYttl374;
ARCHITECTUREusing_1164OFttl374IS
--internalflip-flopoutputs
SIGNALqint:
std_logic_vector（7DOWNTO0）;
BEGIN
qint<=dataWHENrising_edge（clock）;--d-typeflipflops
qout<=qintWHENoebar='0'ELSE"ZZZZZZZZ";--three-statebuffers
ENDARCHITECTUREusing_1164;
Exclusive-ORGate（Dataflowstyle）
--2inputexclusiveor
--ModeledattheRTLlevel.
entityx_oris
port（
in1:
inbit;
in2:
inbit;
out1:
outbit）;
endx_or;
architecturertlofx_oris
begin
out1<=in1xorin2after10ns;
endrtl;
Exclusive-ORGate（Behaviouralstyle）
--Exclusiveorgate
--modeledatthebehaviorallevel.
entityx_oris
port（
in1:
inbit;
in2:
inbit;
out1:
outbit）;
endx_or;
architecturebehaviorofx_oris
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ExamplesofVHDLDescriptions
begin
process（in1,in2）
begin
ifin1=in2then
out1<='0'after10ns;
elseout1<='1'after10ns;
endif;
endprocess;
endbehavior;
Exclusive-ORGate（Structuralstyle）
--2inputexclusive-orgate.
--Modeledatthestructurallevel.
entityx_oris
port（
in1:
inbit;
in2:
inbit;
out1:
outbit）;
endx_or;
entityand_gateis
port（
a:
inbit;
b:
inbit;
c:
outbit）;
endand_gate;
architecturebehaviorofand_gateis
begin
process（a,b）
begin
c<=aandbafter5ns;
endprocess;
endbehavior;
entityor_gateis
port（
d:
inbit;
e:
inbit;
f:
outbit）;
endor_gate;
architecturebehaviorofor_gateis
begin
process（d,e）
begin
f<=doreafter4ns;
endprocess;
endbehavior;
entityinverteris
port（
g:
inbit;
h:
outbit）;
endinverter;
architecturebehaviorofinverteris
begin
process（g）
begin
h<=notgafter3ns;
endprocess;
endbehavior;
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ExamplesofVHDLDescriptions
architecturestructuralofx_oris
--signaldeclarations
signalt1,t2,t3,t4:
bit;
--localcomponentdeclarations
componentand_gate
port（a,b:
inbit;c:
outbit）;
endcomponent;
componentor_gate
port（d,e:
inbit;f:
outbit）;
endcomponent;
componentinverter
port（g:
inbit;h:
outbit）;
endcomponent;
begin
--componentinstantiationstatements
u0:
and_gateportmap（a=>t1,b=>in2,c=>t3）;
u1:
and_gateportmap（a=>in1,b=>t2,c=>t4）;
u2:
inverterportmap（g=>in1,h=>t1）;
u3:
inverterportmap（g=>in2,h=>t2）;
u4:
or_gateportmap（d=>t3,e=>t4,f=>out1）;
endstructural;
Three-inputMajorityVoter
Theentitydeclarationisfollowedbythreealternativearchitectureswhichachievethesamefunctionalityindifferentways.
ENTITYmajIS
PORT（a,b,c:
INBIT;m:
OUTBIT）;
ENDmaj;
--Dataflowstylearchitecture
ARCHITECTUREconcurrentOFmajIS
BEGIN
--selectedsignalassignmentstatement（concurrent）
WITHa&b&cSELECT
m<='1'WHEN"110"|"101"|"011"|"111",'0'WHENOTHERS;
ENDconcurrent;
--Structuralstylearchitecture
ARCHITECTUREstructureOFmajIS
--declarecomponentsusedinarchitecture
COMPONENTand2PORT（in1,in2:
INBIT;out1:
OUTBIT）;
ENDCOMPONENT;
COMPONENTor3PORT（in1,in2,in3:
INBIT;out1:
OUTBIT）;
ENDCOMPONENT;
--declarelocalsignals
SIGNALw1,w2,w3:
BIT;
BEGIN
--componentinstantiationstatements.
--portsofcomponentaremappedtosignals
--withinarchitecturebyposition.
gate1:
and2PORTMAP（a,b,w1）;
gate2:
and2PORTMAP（b,c,w2）;
gate3:
and2PORTMAP（a,c,w3）;
gate4:
or3PORTMAP（w1,
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